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e2211743 WD |
1 | /* |
2 | * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de> | |
3 | * | |
4 | * This file is based on similar values for other boards found in | |
5 | * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /* | |
27 | * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash. | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
e2211743 WD |
33 | /*----------------------------------------------------------------------- |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
39 | #define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */ | |
40 | ||
9c4c5ae3 JL |
41 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
42 | ||
e2211743 WD |
43 | /*----------------------------------------------------------------------- |
44 | * select serial console configuration | |
45 | * | |
46 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
47 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
48 | * for SCC). | |
49 | * | |
50 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
51 | * defined elsewhere (for example, on the cogent platform, there are serial | |
52 | * ports on the motherboard which are used for the serial console - see | |
53 | * cogent/cma101/serial.[ch]). | |
54 | */ | |
55 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
56 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
57 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
58 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
59 | ||
60 | /*----------------------------------------------------------------------- | |
61 | * select ethernet configuration | |
62 | * | |
63 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
64 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
65 | * for FCC) | |
66 | * | |
67 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 68 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
e2211743 WD |
69 | */ |
70 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
71 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
72 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
73 | #define CONFIG_ETHER_INDEX 3 /* which channel for ether */ | |
74 | ||
75 | #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) | |
76 | ||
77 | /*----------------------------------------------------------------------- | |
78 | * - Rx-CLK is CLK14 | |
79 | * - Tx-CLK is CLK16 | |
80 | * - Select bus for bd/buffers (see 28-13) | |
81 | * - Half duplex | |
82 | */ | |
6d0f6bcf JCPV |
83 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) |
84 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) | |
85 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
86 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
e2211743 WD |
87 | |
88 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
89 | ||
90 | /* other options */ | |
91 | ||
92 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
93 | #define CONFIG_BAUDRATE 19200 | |
94 | ||
7be044e4 JL |
95 | /* |
96 | * BOOTP options | |
97 | */ | |
98 | #define CONFIG_BOOTP_SUBNETMASK | |
99 | #define CONFIG_BOOTP_GATEWAY | |
100 | #define CONFIG_BOOTP_HOSTNAME | |
101 | #define CONFIG_BOOTP_BOOTPATH | |
102 | #define CONFIG_BOOTP_BOOTFILESIZE | |
e2211743 WD |
103 | |
104 | /* | |
105 | * select i2c support configuration | |
106 | * | |
107 | * Supported configurations are {none, software, hardware} drivers. | |
108 | * If the software driver is chosen, there are some additional | |
109 | * configuration items that the driver uses to drive the port pins. | |
110 | */ | |
111 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
112 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
114 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
e2211743 WD |
115 | |
116 | /* | |
117 | * Software (bit-bang) I2C driver configuration | |
118 | */ | |
119 | #ifdef CONFIG_SOFT_I2C | |
120 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
121 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
122 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
123 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
124 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
125 | else iop->pdat &= ~0x00010000 | |
126 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
127 | else iop->pdat &= ~0x00020000 | |
128 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
129 | #endif /* CONFIG_SOFT_I2C */ | |
130 | ||
e2211743 | 131 | |
348f258f JL |
132 | /* |
133 | * Command line configuration. | |
134 | */ | |
135 | #include <config_cmd_default.h> | |
e2211743 WD |
136 | |
137 | ||
138 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
139 | #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ | |
140 | #define CONFIG_BOOTARGS "root=/dev/ram rw" | |
141 | ||
348f258f | 142 | #if defined(CONFIG_CMD_KGDB) |
e2211743 WD |
143 | #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
144 | #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ | |
145 | #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ | |
146 | #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ | |
147 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ | |
148 | #endif | |
149 | ||
150 | #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ | |
151 | ||
152 | /*----------------------------------------------------------------------- | |
153 | * Miscellaneous configurable options | |
154 | */ | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
156 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
348f258f | 157 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 158 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
e2211743 | 159 | #else |
6d0f6bcf | 160 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e2211743 | 161 | #endif |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
163 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
164 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
e2211743 | 165 | |
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
167 | #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */ | |
e2211743 WD |
168 | |
169 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */ | |
170 | /* for versions < 2.4.5-pre5 */ | |
171 | ||
6d0f6bcf | 172 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
e2211743 | 173 | |
6d0f6bcf | 174 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
e2211743 | 175 | |
6d0f6bcf | 176 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
e2211743 | 177 | |
6d0f6bcf | 178 | #define CONFIG_SYS_RESET_ADDRESS 0x04400000 |
e2211743 WD |
179 | |
180 | #define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */ | |
181 | ||
182 | /*----------------------------------------------------------------------- | |
183 | * For booting Linux, the board info and command line data | |
184 | * have to be in the first 8 MB of memory, since this is | |
185 | * the maximum mapped by the Linux kernel during initialization. | |
186 | */ | |
6d0f6bcf | 187 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
e2211743 WD |
188 | |
189 | /*----------------------------------------------------------------------- | |
190 | * Start addresses for the final memory configuration (Setup by the | |
6d0f6bcf | 191 | * startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0. |
e2211743 | 192 | */ |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
194 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 | |
e2211743 | 195 | |
14d0a02a | 196 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
198 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
e2211743 WD |
199 | |
200 | /*----------------------------------------------------------------------- | |
201 | * FLASH organization | |
202 | */ | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
204 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */ | |
205 | #define CONFIG_SYS_MAX_FLASH_SIZE (CONFIG_SYS_MAX_FLASH_SECT * 0x10000) /* 4 MB */ | |
e2211743 | 206 | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */ |
208 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
e2211743 WD |
209 | |
210 | /* Environment in FLASH, there is little space left in Serial EEPROM */ | |
5a1aceb0 | 211 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 212 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ |
6d0f6bcf | 213 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */ |
e2211743 WD |
214 | |
215 | ||
216 | /*----------------------------------------------------------------------- | |
217 | * Hard Reset Configuration Words | |
218 | * | |
6d0f6bcf | 219 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
e2211743 | 220 | * defines for the various registers affected by the HRCW e.g. changing |
6d0f6bcf | 221 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
e2211743 | 222 | */ |
6d0f6bcf | 223 | #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\ |
e2211743 WD |
224 | ( HRCW_L2CPC10 | HRCW_ISB110 ) |\ |
225 | ( HRCW_MMR11 | HRCW_APPC10 ) |\ | |
226 | ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ | |
227 | ) /* 0x14863245 */ | |
228 | ||
229 | /* no slaves */ | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
231 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
232 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
233 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
234 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
235 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
236 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
e2211743 WD |
237 | |
238 | /*----------------------------------------------------------------------- | |
239 | * Internal Memory Mapped Register | |
240 | */ | |
6d0f6bcf | 241 | #define CONFIG_SYS_IMMR 0xFF000000 /* We keep original value */ |
e2211743 WD |
242 | |
243 | /*----------------------------------------------------------------------- | |
244 | * Definitions for initial stack pointer and data area (in DPRAM) | |
245 | */ | |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
247 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
248 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
249 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
250 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
e2211743 WD |
251 | |
252 | /*----------------------------------------------------------------------- | |
253 | * Internal Definitions | |
254 | * | |
255 | * Boot Flags | |
256 | */ | |
257 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
258 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
259 | ||
260 | ||
261 | /*----------------------------------------------------------------------- | |
262 | * Cache Configuration | |
263 | */ | |
6d0f6bcf | 264 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
348f258f | 265 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 266 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
e2211743 WD |
267 | #endif |
268 | ||
269 | /*----------------------------------------------------------------------- | |
270 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
271 | *----------------------------------------------------------------------- | |
272 | * HID0 also contains cache control. | |
273 | * | |
274 | * HID1 has only read-only information - nothing to set. | |
275 | */ | |
6d0f6bcf | 276 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
53677ef1 | 277 | HID0_IFEM|HID0_ABE) |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) |
279 | #define CONFIG_SYS_HID2 0 | |
e2211743 WD |
280 | |
281 | /*----------------------------------------------------------------------- | |
282 | * RMR - Reset Mode Register 5-5 | |
283 | *----------------------------------------------------------------------- | |
284 | * turn on Checkstop Reset Enable | |
285 | */ | |
6d0f6bcf | 286 | #define CONFIG_SYS_RMR RMR_CSRE |
e2211743 WD |
287 | |
288 | /*----------------------------------------------------------------------- | |
289 | * BCR - Bus Configuration 4-25 | |
290 | *----------------------------------------------------------------------- | |
291 | */ | |
6d0f6bcf | 292 | #define CONFIG_SYS_BCR 0xA01C0000 |
e2211743 WD |
293 | |
294 | /*----------------------------------------------------------------------- | |
295 | * SIUMCR - SIU Module Configuration 4-31 | |
296 | *----------------------------------------------------------------------- | |
297 | */ | |
6d0f6bcf | 298 | #define CONFIG_SYS_SIUMCR 0X4205C000 |
e2211743 WD |
299 | |
300 | /*----------------------------------------------------------------------- | |
301 | * SYPCR - System Protection Control 4-35 | |
302 | * SYPCR can only be written once after reset! | |
303 | *----------------------------------------------------------------------- | |
304 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
305 | */ | |
306 | #if defined (CONFIG_WATCHDOG) | |
6d0f6bcf | 307 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
e2211743 WD |
308 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
309 | #else | |
6d0f6bcf | 310 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
e2211743 WD |
311 | SYPCR_SWRI|SYPCR_SWP) |
312 | #endif /* CONFIG_WATCHDOG */ | |
313 | ||
314 | /*----------------------------------------------------------------------- | |
315 | * TMCNTSC - Time Counter Status and Control 4-40 | |
316 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
317 | * and enable Time Counter | |
318 | *----------------------------------------------------------------------- | |
319 | */ | |
6d0f6bcf | 320 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
e2211743 WD |
321 | |
322 | /*----------------------------------------------------------------------- | |
323 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
324 | *----------------------------------------------------------------------- | |
325 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
326 | * Periodic timer | |
327 | */ | |
6d0f6bcf | 328 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
e2211743 WD |
329 | |
330 | /*----------------------------------------------------------------------- | |
331 | * SCCR - System Clock Control 9-8 | |
332 | *----------------------------------------------------------------------- | |
333 | * Ensure DFBRG is Divide by 16 | |
334 | */ | |
6d0f6bcf | 335 | #define CONFIG_SYS_SCCR 0 |
e2211743 WD |
336 | |
337 | /*----------------------------------------------------------------------- | |
338 | * RCCR - RISC Controller Configuration 13-7 | |
339 | *----------------------------------------------------------------------- | |
340 | */ | |
6d0f6bcf | 341 | #define CONFIG_SYS_RCCR 0 |
e2211743 WD |
342 | |
343 | /*----------------------------------------------------------------------- | |
344 | * Init Memory Controller: | |
345 | * | |
346 | * Bank Bus Machine PortSz Device | |
347 | * ---- --- ------- ------ ------ | |
348 | * 0 60x GPCM 64 bit FLASH | |
349 | * 1 60x SDRAM 64 bit SDRAM | |
350 | */ | |
351 | ||
6d0f6bcf JCPV |
352 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801) |
353 | #define CONFIG_SYS_OR0_PRELIM 0xFF800882 | |
354 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041) | |
355 | #define CONFIG_SYS_OR1_PRELIM 0xF8002CD0 | |
e2211743 | 356 | |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_PSDMR 0x404A241A |
358 | #define CONFIG_SYS_MPTPR 0x00007400 | |
359 | #define CONFIG_SYS_PSRT 0x00000007 | |
e2211743 WD |
360 | |
361 | #endif /* __CONFIG_H */ |