[people/ms/u-boot.git] / include / configs / ISPAN.h

/*
 * Copyright (C) 2004 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 *
 * Support for Interphase iSPAN Communications Controllers
 * (453x and others). Tested on 4532.
 *
 * Derived from iSPAN 4539 port (iphase4539) by
 * Wolfgang Grandegger <wg@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MPC8260			/* This is an MPC8260 CPU               */
#define CONFIG_ISPAN			/* ...on one of Interphase iSPAN boards */
#define CONFIG_CPM2		1	/* Has a CPM2 */

#define	CONFIG_SYS_TEXT_BASE	0xFE7A0000

/*-----------------------------------------------------------------------
 * Select serial console configuration
 *
 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * If CONFIG_CONS_NONE is defined, then the serial console routines must be
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define	CONFIG_CONS_ON_SMC		/* Define if console on SMC		*/
#undef	CONFIG_CONS_ON_SCC		/* Define if console on SCC		*/
#undef	CONFIG_CONS_NONE		/* Define if console on something else	*/
#define CONFIG_CONS_INDEX	1	/* Which serial channel for console	*/

/*-----------------------------------------------------------------------
 * Select Ethernet configuration
 *
 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC).
 *
 * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
 * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* Define if Ethernet on SCC		*/
#define CONFIG_ETHER_ON_FCC		/* Define if Ethernet on FCC		*/
#undef	CONFIG_ETHER_NONE		/* Define if Ethernet on something else */
#define CONFIG_ETHER_INDEX	3	/* Which channel for Ethernrt		*/

#ifdef CONFIG_ETHER_ON_FCC

#if CONFIG_ETHER_INDEX == 3

#define CONFIG_SYS_PHY_ADDR		0
#define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
#define CONFIG_SYS_CMXFCR_MASK3		(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)

#endif /* CONFIG_ETHER_INDEX == 3 */

#define CONFIG_SYS_CPMFCR_RAMTYPE	0
#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#define CONFIG_MII				/* MII PHY management		*/
#define CONFIG_BITBANGMII			/* Bit-bang MII PHY management	*/
/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT		3		/* Port D */
#define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
#define MDC_DECLARE		MDIO_DECLARE


#define CONFIG_SYS_MDIO_PIN		0x00040000	/* PD13 */
#define CONFIG_SYS_MDC_PIN		0x00080000	/* PD12 */

#define MDIO_ACTIVE		(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
#define MDIO_TRISTATE		(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
#define MDIO_READ		((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)

#define MDIO(bit)		if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
				else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN

#define MDC(bit)		if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
				else	iop->pdat &= ~CONFIG_SYS_MDC_PIN

#define MIIDELAY		udelay(1)

#endif /* CONFIG_ETHER_ON_FCC */

#define CONFIG_8260_CLKIN	65536000	/* in Hz */
#define CONFIG_BAUDRATE		38400


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO


#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds	*/
#define CONFIG_BOOTCOMMAND	"bootm fe010000"	/* autoboot command	*/
#define CONFIG_BOOTARGS		"root=/dev/ram rw"

#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
#undef	CONFIG_WATCHDOG		/* Disable platform specific watchdog		*/

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x03B00000	/* 1 ... 59 MB in SDRAM		*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* Default load address		*/

#define CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_RESET_ADDRESS	0x09900000

#define CONFIG_MISC_INIT_R			/* We need misc_init_r()	*/

/*-----------------------------------------------------------------------
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor   */
#ifdef CONFIG_BZIP2
#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()    */
#else
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
#endif /* CONFIG_BZIP2 */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max num of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	142		/* Max num of sects on one chip */

/* Environment is in flash, there is little space left in Serial EEPROM */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000		/* We use one complete sector	*/
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * If you change bits in the HRCW, you must also change the CONFIG_SYS_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 */
/* 0x1686B245 */
#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM      | HRCW_BPS01       | HRCW_CIP    |\
			 HRCW_L2CPC10  | HRCW_ISB110                    |\
			 HRCW_BMS      | HRCW_MMR11       | HRCW_APPC10 |\
			 HRCW_CS10PC01 | HRCW_MODCK_H0101                \
			)
/* No slaves */
#define CONFIG_SYS_HRCW_SLAVE1 0
#define CONFIG_SYS_HRCW_SLAVE2 0
#define CONFIG_SYS_HRCW_SLAVE3 0
#define CONFIG_SYS_HRCW_SLAVE4 0
#define CONFIG_SYS_HRCW_SLAVE5 0
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0F00000
#ifdef CONFIG_SYS_REV_B
#define CONFIG_SYS_DEFAULT_IMMR	0xFF000000
#endif /* CONFIG_SYS_REV_B */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers		2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT		(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
				HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL		(HID0_ICE|HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID2		0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register					 5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR			RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration					 4-25
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_BCR			0xA01C0000

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				 4-31
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SIUMCR		0x42250000/* 0x4205C000 */

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				 4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined (CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
				SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CONFIG_SYS_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
				SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control			 4-40
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control					 9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CONFIG_SYS_SCCR		SCCR_DFBRG01

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration				13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR		0

/*-----------------------------------------------------------------------
 * Init Memory Controller:
 *
 * Bank Bus	Machine PortSize                        Device
 * ---- ---	------- -----------------------------   ------
 *  0	60x	GPCM	 8 bit (Rev.B)/16 bit (Rev.D)   Flash
 *  1	60x	SDRAM	64 bit                          SDRAM
 *  2	Local	SDRAM	32 bit	                        SDRAM
 */
#define CONFIG_SYS_USE_FIRMWARE	/* If defined - do not initialise memory
				   controller, rely on initialisation
				   performed by the Interphase boot firmware.
				 */

#define CONFIG_SYS_OR0_PRELIM		0xFE000882
#ifdef CONFIG_SYS_REV_B
#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BRx_PS_8  | BRx_V)
#else  /* Rev. D */
#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
#endif /* CONFIG_SYS_REV_B */

#define CONFIG_SYS_MPTPR		0x7F00

/* Please note that 60x SDRAM MUST start at 0 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_60x_BR		0x00000041
#define CONFIG_SYS_60x_OR		0xF0002CD0
#define CONFIG_SYS_PSDMR		0x0049929A
#define CONFIG_SYS_PSRT		0x07

#define CONFIG_SYS_LSDRAM_BASE		0xF7000000
#define CONFIG_SYS_LOC_BR		0x00001861
#define CONFIG_SYS_LOC_OR		0xFF803280
#define CONFIG_SYS_LSDMR		0x8285A552
#define CONFIG_SYS_LSRT		0x07

#endif /* __CONFIG_H */
Commit	Line	Data
c3c7f861 WD	1	/*
	2	* Copyright (C) 2004 Arabella Software Ltd.
	3	* Yuli Barcohen <yuli@arabellasw.com>
	4	*
	5	* Support for Interphase iSPAN Communications Controllers
	6	* (453x and others). Tested on 4532.
	7	*
	8	* Derived from iSPAN 4539 port (iphase4539) by
	9	* Wolfgang Grandegger <wg@denx.de>
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
c3c7f861 WD	12	*/
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	#define CONFIG_MPC8260 /* This is an MPC8260 CPU */
	17	#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
9c4c5ae3	18	#define CONFIG_CPM2 1 /* Has a CPM2 */
c3c7f861	19
2ae18241 WD	20	#define CONFIG_SYS_TEXT_BASE 0xFE7A0000
2ae18241 WD	21
c3c7f861 WD	22	/*-----------------------------------------------------------------------
	23	* Select serial console configuration
	24	*
	25	* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	26	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	27	* for SCC).
	28	*
	29	* If CONFIG_CONS_NONE is defined, then the serial console routines must be
	30	* defined elsewhere (for example, on the cogent platform, there are serial
	31	* ports on the motherboard which are used for the serial console - see
	32	* cogent/cma101/serial.[ch]).
	33	*/
	34	#define CONFIG_CONS_ON_SMC /* Define if console on SMC */
	35	#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
	36	#undef CONFIG_CONS_NONE /* Define if console on something else */
	37	#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
	38
	39	/*-----------------------------------------------------------------------
	40	* Select Ethernet configuration
	41	*
	42	* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	43	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	44	* for FCC).
	45	*
	46	* If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
639221c7	47	* be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
c3c7f861 WD	48	*/
	49	#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
	50	#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
	51	#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
	52	#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
	53
	54	#ifdef CONFIG_ETHER_ON_FCC
	55
	56	#if CONFIG_ETHER_INDEX == 3
	57
6d0f6bcf	58	#define CONFIG_SYS_PHY_ADDR 0
d4590da4 MF	59	#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 \| CMXFCR_TF3CS_CLK16)
d4590da4 MF	60	#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 \| CMXFCR_RF3CS_MSK \| CMXFCR_TF3CS_MSK)
c3c7f861 WD	61
	62	#endif /* CONFIG_ETHER_INDEX == 3 */
	63
6d0f6bcf JCPV	64	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
6d0f6bcf JCPV	65	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
c3c7f861 WD	66
	67	#define CONFIG_MII /* MII PHY management */
	68	#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
	69	/*
	70	* GPIO pins used for bit-banged MII communications
	71	*/
	72	#define MDIO_PORT 3 /* Port D */
be225442 LCM	73	#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
	74	(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
	75	#define MDC_DECLARE MDIO_DECLARE
	76
c3c7f861	77
6d0f6bcf JCPV	78	#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */
6d0f6bcf JCPV	79	#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */
c3c7f861	80
6d0f6bcf JCPV	81	#define MDIO_ACTIVE (iop->pdir \|= CONFIG_SYS_MDIO_PIN)
	82	#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
	83	#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
c3c7f861	84
6d0f6bcf JCPV	85	#define MDIO(bit) if(bit) iop->pdat \|= CONFIG_SYS_MDIO_PIN; \
6d0f6bcf JCPV	86	else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
c3c7f861	87
6d0f6bcf JCPV	88	#define MDC(bit) if(bit) iop->pdat \|= CONFIG_SYS_MDC_PIN; \
6d0f6bcf JCPV	89	else iop->pdat &= ~CONFIG_SYS_MDC_PIN
c3c7f861 WD	90
	91	#define MIIDELAY udelay(1)
	92
	93	#endif /* CONFIG_ETHER_ON_FCC */
	94
	95	#define CONFIG_8260_CLKIN 65536000 /* in Hz */
	96	#define CONFIG_BAUDRATE 38400
	97
348f258f	98
11799434 JL	99	/*
	100	* BOOTP options
	101	*/
	102	#define CONFIG_BOOTP_BOOTFILESIZE
	103	#define CONFIG_BOOTP_BOOTPATH
	104	#define CONFIG_BOOTP_GATEWAY
	105	#define CONFIG_BOOTP_HOSTNAME
	106
	107
348f258f JL	108	/*
	109	* Command line configuration.
	110	*/
	111	#include <config_cmd_default.h>
	112
	113	#define CONFIG_CMD_ASKENV
	114	#define CONFIG_CMD_DHCP
	115	#define CONFIG_CMD_IMMAP
	116	#define CONFIG_CMD_MII
	117	#define CONFIG_CMD_PING
	118	#define CONFIG_CMD_REGINFO
	119
c3c7f861 WD	120
	121	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	122	#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
	123	#define CONFIG_BOOTARGS "root=/dev/ram rw"
	124
	125	#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
	126	#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
	127
	128	/*-----------------------------------------------------------------------
	129	* Miscellaneous configurable options
	130	*/
6d0f6bcf JCPV	131	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
6d0f6bcf JCPV	132	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	133	#define CONFIG_SYS_LONGHELP /* #undef to save memory */
	134	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	135	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
	136	#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
	137	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c3c7f861	138
6d0f6bcf JCPV	139	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	140	#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
c3c7f861	141
6d0f6bcf	142	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */
c3c7f861	143
6d0f6bcf	144	#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */
c3c7f861	145
6d0f6bcf	146	#define CONFIG_SYS_RESET_ADDRESS 0x09900000
c3c7f861 WD	147
	148	#define CONFIG_MISC_INIT_R /* We need misc_init_r() */
	149
	150	/*-----------------------------------------------------------------------
	151	* For booting Linux, the board info and command line data
	152	* have to be in the first 8 MB of memory, since this is
	153	* the maximum mapped by the Linux kernel during initialization.
	154	*/
6d0f6bcf	155	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c3c7f861	156
14d0a02a	157	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf	158	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
c3c7f861	159	#ifdef CONFIG_BZIP2
6d0f6bcf	160	#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
c3c7f861	161	#else
6d0f6bcf	162	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
c3c7f861 WD	163	#endif /* CONFIG_BZIP2 */
	164
	165	/*-----------------------------------------------------------------------
	166	* FLASH organization
	167	*/
6d0f6bcf JCPV	168	#define CONFIG_SYS_FLASH_BASE 0xFE000000
6d0f6bcf JCPV	169	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	170	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
6d0f6bcf JCPV	171	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */
6d0f6bcf JCPV	172	#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
c3c7f861 WD	173
c3c7f861 WD	174	/* Environment is in flash, there is little space left in Serial EEPROM */
5a1aceb0	175	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	176	#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
0e8d1586 JCPV	177	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf	178	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
0e8d1586 JCPV	179	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	180	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
c3c7f861 WD	181
	182	/*-----------------------------------------------------------------------
	183	* Hard Reset Configuration Words
	184	*
6d0f6bcf	185	* If you change bits in the HRCW, you must also change the CONFIG_SYS_*
c3c7f861	186	* defines for the various registers affected by the HRCW e.g. changing
6d0f6bcf	187	* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
c3c7f861 WD	188	*/
c3c7f861 WD	189	/* 0x1686B245 */
6d0f6bcf	190	#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM \| HRCW_BPS01 \| HRCW_CIP \|\
c3c7f861 WD	191	HRCW_L2CPC10 \| HRCW_ISB110 \|\
	192	HRCW_BMS \| HRCW_MMR11 \| HRCW_APPC10 \|\
	193	HRCW_CS10PC01 \| HRCW_MODCK_H0101 \
	194	)
	195	/* No slaves */
6d0f6bcf JCPV	196	#define CONFIG_SYS_HRCW_SLAVE1 0
	197	#define CONFIG_SYS_HRCW_SLAVE2 0
	198	#define CONFIG_SYS_HRCW_SLAVE3 0
	199	#define CONFIG_SYS_HRCW_SLAVE4 0
	200	#define CONFIG_SYS_HRCW_SLAVE5 0
	201	#define CONFIG_SYS_HRCW_SLAVE6 0
	202	#define CONFIG_SYS_HRCW_SLAVE7 0
c3c7f861 WD	203
	204	/*-----------------------------------------------------------------------
	205	* Internal Memory Mapped Register
	206	*/
6d0f6bcf JCPV	207	#define CONFIG_SYS_IMMR 0xF0F00000
	208	#ifdef CONFIG_SYS_REV_B
	209	#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000
	210	#endif /* CONFIG_SYS_REV_B */
c3c7f861 WD	211	/*-----------------------------------------------------------------------
	212	* Definitions for initial stack pointer and data area (in DPRAM)
	213	*/
6d0f6bcf	214	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	215	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
25ddd1fb	216	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	217	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c3c7f861	218
c3c7f861 WD	219	/*-----------------------------------------------------------------------
	220	* Cache Configuration
	221	*/
6d0f6bcf	222	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
c3c7f861 WD	223
	224	/*-----------------------------------------------------------------------
	225	* HIDx - Hardware Implementation-dependent Registers 2-11
	226	*-----------------------------------------------------------------------
	227	* HID0 also contains cache control.
	228	*
	229	* HID1 has only read-only information - nothing to set.
	230	*/
6d0f6bcf	231	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI\|\
c3c7f861	232	HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	233	#define CONFIG_SYS_HID0_FINAL (HID0_ICE\|HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	234	#define CONFIG_SYS_HID2 0
c3c7f861 WD	235
	236	/*-----------------------------------------------------------------------
	237	* RMR - Reset Mode Register 5-5
	238	*-----------------------------------------------------------------------
	239	* turn on Checkstop Reset Enable
	240	*/
6d0f6bcf	241	#define CONFIG_SYS_RMR RMR_CSRE
c3c7f861 WD	242
	243	/*-----------------------------------------------------------------------
	244	* BCR - Bus Configuration 4-25
	245	*-----------------------------------------------------------------------
	246	*/
6d0f6bcf	247	#define CONFIG_SYS_BCR 0xA01C0000
c3c7f861 WD	248
	249	/*-----------------------------------------------------------------------
	250	* SIUMCR - SIU Module Configuration 4-31
	251	*-----------------------------------------------------------------------
	252	*/
6d0f6bcf	253	#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */
c3c7f861 WD	254
	255	/*-----------------------------------------------------------------------
	256	* SYPCR - System Protection Control 4-35
	257	* SYPCR can only be written once after reset!
	258	*-----------------------------------------------------------------------
	259	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	260	*/
	261	#if defined (CONFIG_WATCHDOG)
6d0f6bcf	262	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
c3c7f861 WD	263	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
c3c7f861 WD	264	#else
6d0f6bcf	265	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
c3c7f861 WD	266	SYPCR_SWRI\|SYPCR_SWP)
	267	#endif /* CONFIG_WATCHDOG */
	268
	269	/*-----------------------------------------------------------------------
	270	* TMCNTSC - Time Counter Status and Control 4-40
	271	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	272	* and enable Time Counter
	273	*-----------------------------------------------------------------------
	274	*/
6d0f6bcf	275	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
c3c7f861 WD	276
	277	/*-----------------------------------------------------------------------
	278	* PISCR - Periodic Interrupt Status and Control 4-42
	279	*-----------------------------------------------------------------------
	280	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	281	* Periodic timer
	282	*/
6d0f6bcf	283	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
c3c7f861 WD	284
	285	/*-----------------------------------------------------------------------
	286	* SCCR - System Clock Control 9-8
	287	*-----------------------------------------------------------------------
	288	* Ensure DFBRG is Divide by 16
	289	*/
6d0f6bcf	290	#define CONFIG_SYS_SCCR SCCR_DFBRG01
c3c7f861 WD	291
	292	/*-----------------------------------------------------------------------
	293	* RCCR - RISC Controller Configuration 13-7
	294	*-----------------------------------------------------------------------
	295	*/
6d0f6bcf	296	#define CONFIG_SYS_RCCR 0
c3c7f861 WD	297
	298	/*-----------------------------------------------------------------------
	299	* Init Memory Controller:
	300	*
	301	* Bank Bus Machine PortSize Device
	302	* ---- --- ------- ----------------------------- ------
	303	* 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
	304	* 1 60x SDRAM 64 bit SDRAM
	305	* 2 Local SDRAM 32 bit SDRAM
	306	*/
6d0f6bcf	307	#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory
c3c7f861 WD	308	controller, rely on initialisation
	309	performed by the Interphase boot firmware.
	310	*/
	311
6d0f6bcf JCPV	312	#define CONFIG_SYS_OR0_PRELIM 0xFE000882
	313	#ifdef CONFIG_SYS_REV_B
	314	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| BRx_PS_8 \| BRx_V)
c3c7f861	315	#else /* Rev. D */
6d0f6bcf JCPV	316	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| BRx_PS_16 \| BRx_V)
6d0f6bcf JCPV	317	#endif /* CONFIG_SYS_REV_B */
c3c7f861	318
6d0f6bcf	319	#define CONFIG_SYS_MPTPR 0x7F00
c3c7f861 WD	320
c3c7f861 WD	321	/* Please note that 60x SDRAM MUST start at 0 */
6d0f6bcf JCPV	322	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	323	#define CONFIG_SYS_60x_BR 0x00000041
	324	#define CONFIG_SYS_60x_OR 0xF0002CD0
	325	#define CONFIG_SYS_PSDMR 0x0049929A
	326	#define CONFIG_SYS_PSRT 0x07
	327
	328	#define CONFIG_SYS_LSDRAM_BASE 0xF7000000
	329	#define CONFIG_SYS_LOC_BR 0x00001861
	330	#define CONFIG_SYS_LOC_OR 0xFF803280
	331	#define CONFIG_SYS_LSDMR 0x8285A552
	332	#define CONFIG_SYS_LSRT 0x07
c3c7f861 WD	333
c3c7f861 WD	334	#endif /* __CONFIG_H */