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0f8c9768 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ | |
37 | #define CONFIG_IVML24 1 /* ...on a IVML24 board */ | |
38 | ||
39 | #if defined (CONFIG_IVML24_16M) | |
40 | # define CONFIG_IDENT_STRING " IVML24" | |
41 | #elif defined (CONFIG_IVML24_32M) | |
42 | # define CONFIG_IDENT_STRING " IVML24_128" | |
43 | #elif defined (CONFIG_IVML24_64M) | |
44 | # define CONFIG_IDENT_STRING " IVML24_256" | |
45 | #endif | |
46 | ||
47 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
48 | #undef CONFIG_8xx_CONS_SMC2 | |
49 | #undef CONFIG_8xx_CONS_NONE | |
50 | #define CONFIG_BAUDRATE 115200 | |
51 | ||
52 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
53 | #define CONFIG_8xx_GCLK_FREQ 50331648 | |
54 | ||
55 | #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ | |
56 | ||
57 | #if 0 | |
58 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
59 | #else | |
60 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
61 | #endif | |
62 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ | |
63 | ||
64 | #define CONFIG_BOOTARGS "root=/dev/nfs rw " \ | |
65 | "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ | |
66 | "nfsaddrs=10.0.0.99:10.0.0.2" | |
67 | ||
68 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 69 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
0f8c9768 WD |
70 | |
71 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
72 | ||
73 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
74 | ||
348f258f JL |
75 | |
76 | /* | |
77 | * Command line configuration. | |
78 | */ | |
79 | #include <config_cmd_default.h> | |
80 | ||
81 | #define CONFIG_CMD_IDE | |
82 | ||
83 | ||
0f8c9768 WD |
84 | #define CONFIG_MAC_PARTITION |
85 | #define CONFIG_DOS_PARTITION | |
86 | ||
7be044e4 JL |
87 | /* |
88 | * BOOTP options | |
89 | */ | |
90 | #define CONFIG_BOOTP_SUBNETMASK | |
91 | #define CONFIG_BOOTP_HOSTNAME | |
92 | #define CONFIG_BOOTP_BOOTPATH | |
93 | #define CONFIG_BOOTP_BOOTFILESIZE | |
94 | ||
0f8c9768 | 95 | |
0f8c9768 WD |
96 | /* |
97 | * Miscellaneous configurable options | |
98 | */ | |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
100 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
348f258f | 101 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 102 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0f8c9768 | 103 | #else |
6d0f6bcf | 104 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0f8c9768 | 105 | #endif |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
107 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
108 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0f8c9768 | 109 | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
111 | #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ | |
0f8c9768 | 112 | |
6d0f6bcf | 113 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
0f8c9768 | 114 | |
6d0f6bcf | 115 | #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
0f8c9768 | 116 | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_PB_12V_ENABLE 0x00002000 /* PB 18 */ |
118 | #define CONFIG_SYS_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */ | |
119 | #define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ | |
120 | #define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ | |
121 | #define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */ | |
0f8c9768 | 122 | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ |
124 | #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ | |
0f8c9768 | 125 | |
6d0f6bcf | 126 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
0f8c9768 | 127 | |
6d0f6bcf | 128 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
0f8c9768 WD |
129 | |
130 | /* | |
131 | * Low Level Configuration Settings | |
132 | * (address mappings, register initial values, etc.) | |
133 | * You should know what you are doing if you make changes here. | |
134 | */ | |
135 | /*----------------------------------------------------------------------- | |
136 | * Internal Memory Mapped Register | |
137 | */ | |
6d0f6bcf | 138 | #define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */ |
0f8c9768 WD |
139 | |
140 | /*----------------------------------------------------------------------- | |
141 | * Definitions for initial stack pointer and data area (in DPRAM) | |
142 | */ | |
6d0f6bcf | 143 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
0f8c9768 WD |
144 | |
145 | #if defined (CONFIG_IVML24_16M) | |
6d0f6bcf | 146 | # define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
0f8c9768 | 147 | #elif defined (CONFIG_IVML24_32M) |
6d0f6bcf | 148 | # define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ |
0f8c9768 | 149 | #elif defined (CONFIG_IVML24_64M) |
6d0f6bcf | 150 | # define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ |
0f8c9768 WD |
151 | #endif |
152 | ||
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
154 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
155 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
0f8c9768 WD |
156 | |
157 | /*----------------------------------------------------------------------- | |
158 | * Start addresses for the final memory configuration | |
159 | * (Set up by the startup code) | |
6d0f6bcf | 160 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
0f8c9768 | 161 | */ |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
163 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
0f8c9768 | 164 | #ifdef DEBUG |
6d0f6bcf | 165 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
0f8c9768 | 166 | #else |
6d0f6bcf | 167 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
0f8c9768 | 168 | #endif |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
170 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
0f8c9768 WD |
171 | |
172 | /* | |
173 | * For booting Linux, the board info and command line data | |
174 | * have to be in the first 8 MB of memory, since this is | |
175 | * the maximum mapped by the Linux kernel during initialization. | |
176 | */ | |
6d0f6bcf | 177 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
0f8c9768 WD |
178 | /*----------------------------------------------------------------------- |
179 | * FLASH organization | |
180 | */ | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
182 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
0f8c9768 | 183 | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
185 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
0f8c9768 | 186 | |
5a1aceb0 | 187 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
188 | #define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ |
189 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
0f8c9768 WD |
190 | /*----------------------------------------------------------------------- |
191 | * Cache Configuration | |
192 | */ | |
6d0f6bcf | 193 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
348f258f | 194 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 195 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
0f8c9768 WD |
196 | #endif |
197 | ||
198 | /*----------------------------------------------------------------------- | |
199 | * SYPCR - System Protection Control 11-9 | |
200 | * SYPCR can only be written once after reset! | |
201 | *----------------------------------------------------------------------- | |
202 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
203 | */ | |
204 | #if defined(CONFIG_WATCHDOG) | |
205 | ||
206 | # if defined (CONFIG_IVML24_16M) | |
6d0f6bcf | 207 | # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
53677ef1 | 208 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
0f8c9768 | 209 | # elif defined (CONFIG_IVML24_32M) |
6d0f6bcf | 210 | # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
0f8c9768 WD |
211 | SYPCR_SWE | SYPCR_SWP) |
212 | # elif defined (CONFIG_IVML24_64M) | |
6d0f6bcf | 213 | # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
0f8c9768 WD |
214 | SYPCR_SWE | SYPCR_SWP) |
215 | # endif | |
216 | ||
217 | #else | |
6d0f6bcf | 218 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
0f8c9768 WD |
219 | #endif |
220 | ||
221 | /*----------------------------------------------------------------------- | |
222 | * SIUMCR - SIU Module Configuration 11-6 | |
223 | *----------------------------------------------------------------------- | |
224 | * PCMCIA config., multi-function pin tri-state | |
225 | */ | |
226 | /* EARB, DBGC and DBPC are initialised by the HCW */ | |
227 | /* => 0x000000C0 */ | |
6d0f6bcf | 228 | #define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) |
0f8c9768 WD |
229 | |
230 | /*----------------------------------------------------------------------- | |
231 | * TBSCR - Time Base Status and Control 11-26 | |
232 | *----------------------------------------------------------------------- | |
233 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
234 | */ | |
6d0f6bcf | 235 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
0f8c9768 WD |
236 | |
237 | /*----------------------------------------------------------------------- | |
238 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
239 | *----------------------------------------------------------------------- | |
240 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
241 | */ | |
6d0f6bcf | 242 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
0f8c9768 WD |
243 | |
244 | /*----------------------------------------------------------------------- | |
245 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
246 | *----------------------------------------------------------------------- | |
247 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
248 | * interrupt status bit, set PLL multiplication factor ! | |
249 | */ | |
250 | /* 0x00B0C0C0 */ | |
6d0f6bcf | 251 | #define CONFIG_SYS_PLPRCR \ |
0f8c9768 WD |
252 | ( (11 << PLPRCR_MF_SHIFT) | \ |
253 | PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ | |
254 | /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ | |
255 | PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ | |
256 | ) | |
257 | ||
258 | /*----------------------------------------------------------------------- | |
259 | * SCCR - System Clock and reset Control Register 15-27 | |
260 | *----------------------------------------------------------------------- | |
261 | * Set clock output, timebase and RTC source and divider, | |
262 | * power management and some other internal clocks | |
263 | */ | |
264 | #define SCCR_MASK SCCR_EBDF11 | |
265 | /* 0x01800014 */ | |
6d0f6bcf | 266 | #define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ |
0f8c9768 | 267 | SCCR_RTDIV | SCCR_RTSEL | \ |
53677ef1 | 268 | /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ |
0f8c9768 WD |
269 | SCCR_EBDF00 | SCCR_DFSYNC00 | \ |
270 | SCCR_DFBRG00 | SCCR_DFNL000 | \ | |
271 | SCCR_DFNH000 | SCCR_DFLCD101 | \ | |
272 | SCCR_DFALCD00) | |
273 | ||
274 | /*----------------------------------------------------------------------- | |
275 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
276 | *----------------------------------------------------------------------- | |
277 | */ | |
278 | /* 0x00C3 */ | |
6d0f6bcf | 279 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
0f8c9768 WD |
280 | |
281 | ||
282 | /*----------------------------------------------------------------------- | |
283 | * RCCR - RISC Controller Configuration Register 19-4 | |
284 | *----------------------------------------------------------------------- | |
285 | */ | |
286 | /* TIMEP=2 */ | |
6d0f6bcf | 287 | #define CONFIG_SYS_RCCR 0x0200 |
0f8c9768 WD |
288 | |
289 | /*----------------------------------------------------------------------- | |
290 | * RMDS - RISC Microcode Development Support Control Register | |
291 | *----------------------------------------------------------------------- | |
292 | */ | |
6d0f6bcf | 293 | #define CONFIG_SYS_RMDS 0 |
0f8c9768 WD |
294 | |
295 | /*----------------------------------------------------------------------- | |
296 | * | |
297 | * Interrupt Levels | |
298 | *----------------------------------------------------------------------- | |
299 | */ | |
6d0f6bcf | 300 | #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ |
0f8c9768 WD |
301 | |
302 | /*----------------------------------------------------------------------- | |
303 | * PCMCIA stuff | |
304 | *----------------------------------------------------------------------- | |
305 | * | |
306 | */ | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
308 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
309 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
310 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
311 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
312 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
313 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
314 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
0f8c9768 WD |
315 | |
316 | /*----------------------------------------------------------------------- | |
317 | * IDE/ATA stuff | |
318 | *----------------------------------------------------------------------- | |
319 | */ | |
320 | #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ | |
321 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ | |
322 | ||
6d0f6bcf JCPV |
323 | #define CONFIG_SYS_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/ |
324 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ | |
0f8c9768 | 325 | |
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000 |
327 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
328 | #undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */ | |
0f8c9768 | 329 | |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
331 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ | |
332 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ | |
0f8c9768 WD |
333 | |
334 | /*----------------------------------------------------------------------- | |
335 | * | |
336 | *----------------------------------------------------------------------- | |
337 | * | |
338 | */ | |
6d0f6bcf | 339 | #define CONFIG_SYS_DER 0 |
0f8c9768 WD |
340 | |
341 | /* | |
342 | * Init Memory Controller: | |
343 | * | |
344 | * BR0 and OR0 (FLASH) | |
345 | */ | |
346 | ||
347 | #define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ | |
348 | ||
349 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
350 | * restrict access enough to keep SRAM working (if any) | |
351 | * but not too much to meddle with FLASH accesses | |
352 | */ | |
353 | /* EPROMs are 512kb */ | |
6d0f6bcf JCPV |
354 | #define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ |
355 | #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ | |
0f8c9768 WD |
356 | |
357 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
6d0f6bcf | 358 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR) |
0f8c9768 | 359 | |
6d0f6bcf JCPV |
360 | #define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \ |
361 | CONFIG_SYS_OR_TIMING_FLASH) | |
362 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \ | |
363 | CONFIG_SYS_OR_TIMING_FLASH) | |
0f8c9768 | 364 | /* 16 bit, bank valid */ |
6d0f6bcf | 365 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
0f8c9768 WD |
366 | |
367 | /* | |
368 | * BR1/OR1 - ELIC SACCO bank @ 0xFE000000 | |
369 | * | |
370 | * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 | |
371 | */ | |
372 | #define ELIC_SACCO_BASE 0xFE000000 | |
373 | #define ELIC_SACCO_OR_AM 0xFFFF8000 | |
374 | #define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) | |
375 | ||
6d0f6bcf | 376 | #define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
0f8c9768 | 377 | ELIC_SACCO_TIMING) |
6d0f6bcf | 378 | #define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
0f8c9768 WD |
379 | |
380 | /* | |
381 | * BR2/OR2 - ELIC EPIC bank @ 0xFE008000 | |
382 | * | |
383 | * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 | |
384 | */ | |
385 | #define ELIC_EPIC_BASE 0xFE008000 | |
386 | #define ELIC_EPIC_OR_AM 0xFFFF8000 | |
387 | #define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) | |
388 | ||
6d0f6bcf | 389 | #define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
0f8c9768 | 390 | ELIC_EPIC_TIMING) |
6d0f6bcf | 391 | #define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
0f8c9768 WD |
392 | |
393 | /* | |
394 | * BR3/OR3: SDRAM | |
395 | * | |
396 | * Multiplexed addresses, GPL5 output to GPL5_A (don't care) | |
397 | */ | |
398 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ | |
399 | #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ | |
400 | #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ | |
401 | ||
402 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ | |
403 | ||
6d0f6bcf JCPV |
404 | #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) |
405 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) | |
0f8c9768 WD |
406 | |
407 | /* | |
408 | * BR4/OR4 - HDLC Address | |
409 | * | |
410 | * AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0 | |
411 | */ | |
412 | #define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */ | |
413 | #define HDLC_ADDR_OR_AM 0xFFFF8000 | |
414 | #define HDLC_ADDR_TIMING OR_SCY_1_CLK | |
415 | ||
6d0f6bcf JCPV |
416 | #define CONFIG_SYS_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING) |
417 | #define CONFIG_SYS_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V ) | |
0f8c9768 WD |
418 | |
419 | /* | |
420 | * BR5/OR5: SHARC ADSP-2165L | |
421 | * | |
422 | * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 | |
423 | */ | |
424 | #define SHARC_BASE 0xFE400000 | |
425 | #define SHARC_OR_AM 0xFFC00000 | |
426 | #define SHARC_TIMING OR_SCY_0_CLK | |
427 | ||
6d0f6bcf JCPV |
428 | #define CONFIG_SYS_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING ) |
429 | #define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) | |
0f8c9768 WD |
430 | |
431 | /* | |
432 | * Memory Periodic Timer Prescaler | |
433 | */ | |
434 | ||
435 | /* periodic timer for refresh */ | |
6d0f6bcf | 436 | #define CONFIG_SYS_MBMR_PTB 204 |
0f8c9768 WD |
437 | |
438 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ | |
6d0f6bcf JCPV |
439 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
440 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
0f8c9768 WD |
441 | |
442 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf | 443 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
0f8c9768 WD |
444 | |
445 | #if defined (CONFIG_IVML24_16M) | |
6d0f6bcf | 446 | # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
0f8c9768 | 447 | #elif defined (CONFIG_IVML24_32M) |
6d0f6bcf | 448 | # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
0f8c9768 | 449 | #elif defined (CONFIG_IVML24_64M) |
6d0f6bcf | 450 | # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ |
0f8c9768 WD |
451 | #endif |
452 | ||
453 | ||
454 | /* | |
455 | * MBMR settings for SDRAM | |
456 | */ | |
457 | ||
458 | #if defined (CONFIG_IVML24_16M) | |
459 | /* 8 column SDRAM */ | |
6d0f6bcf | 460 | # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ |
53677ef1 WD |
461 | MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ |
462 | MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) | |
0f8c9768 WD |
463 | #elif defined (CONFIG_IVML24_32M) |
464 | /* 128 MBit SDRAM */ | |
6d0f6bcf | 465 | # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ |
2535d602 WD |
466 | MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ |
467 | MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) | |
0f8c9768 WD |
468 | #elif defined (CONFIG_IVML24_64M) |
469 | /* 128 MBit SDRAM */ | |
6d0f6bcf | 470 | # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ |
2535d602 WD |
471 | MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ |
472 | MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) | |
0f8c9768 WD |
473 | #endif |
474 | ||
475 | /* | |
476 | * Internal Definitions | |
477 | * | |
478 | * Boot Flags | |
479 | */ | |
480 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
481 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
482 | ||
483 | #endif /* __CONFIG_H */ |