[people/ms/u-boot.git] / include / configs / IceCube.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
#define CONFIG_ICECUBE		1	/* ... on IceCube board */

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFFF00000	boot high (standard configuration)
 * 0xFF000000	boot low for 16 MiB boards
 * 0xFF800000	boot low for  8 MiB boards
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI

#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000
#endif

#define CONFIG_SYS_XLB_PIPELINING	1

#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif


#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
#   define CONFIG_SYS_LOWBOOT	        1
#   define CONFIG_SYS_LOWBOOT16	1
#endif
#if (CONFIG_SYS_TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
#if defined(CONFIG_LITE5200B)
#   error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
#else
#   define CONFIG_SYS_LOWBOOT	        1
#   define CONFIG_SYS_LOWBOOT08	1
#endif
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
#else
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * Flash configuration
 */
#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
#else	/* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_SYS_LOWBOOT08)
# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
#endif
#if defined(CONFIG_SYS_LOWBOOT16)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x01060000)
#endif
#endif /* CONFIG_SYS_LOWBOOT */
#else /* !CONFIG_LITE5200B (IceCube)*/
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
#else	/* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_SYS_LOWBOOT08)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
#endif
#if defined(CONFIG_SYS_LOWBOOT16)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
#endif
#endif	/* CONFIG_SYS_LOWBOOT */
#endif /* CONFIG_LITE5200B */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks      */

#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */

#if defined(CONFIG_LITE5200B)
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
#endif


/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#if defined(CONFIG_LITE5200B)
#define CONFIG_ENV_SECT_SIZE	0x20000
#else
#define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 */
#ifdef CONFIG_MPC5200_DDR
#define CONFIG_SYS_GPS_PORT_CONFIG	0x90000004
#else
#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_CFG		0x00047800
#define CONFIG_SYS_CS0_START		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_CS0_START
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047800
#else /* IceCube aka Lite5200 */
#ifdef CONFIG_MPC5200_DDR

#define CONFIG_SYS_BOOTCS_START	(CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
#define CONFIG_SYS_BOOTCS_SIZE		0x00800000
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE		0x00800000
#define CONFIG_SYS_CS1_CFG		0x00047800

#else /* !CONFIG_MPC5200_DDR */

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#endif /* CONFIG_MPC5200_DDR */
#endif /*CONFIG_LITE5200B */

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#define CONFIG_ATAPI            1

#endif /* __CONFIG_H */
Commit	Line	Data
945af8d7	1	/*
414eec35	2	* (C) Copyright 2003-2005
945af8d7 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
945af8d7 WD	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
945af8d7 WD	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
	14	*/
	15
b2a6dfe4	16	#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
945af8d7 WD	17	#define CONFIG_ICECUBE 1 /* ... on IceCube board */
945af8d7 WD	18
2ae18241 WD	19	/*
	20	* Valid values for CONFIG_SYS_TEXT_BASE are:
	21	* 0xFFF00000 boot high (standard configuration)
	22	* 0xFF000000 boot low for 16 MiB boards
	23	* 0xFF800000 boot low for 8 MiB boards
	24	* 0x00100000 boot from RAM (for testing only)
	25	*/
	26	#ifndef CONFIG_SYS_TEXT_BASE
	27	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	28	#endif
	29
6d0f6bcf	30	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
945af8d7	31
31d82672 BB	32	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	33
945af8d7 WD	34	/*
	35	* Serial console configuration
	36	*/
	37	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	38	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	39	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
945af8d7	40
96e48cf6	41
96e48cf6 WD	42	/*
	43	* PCI Mapping:
	44	* 0x40000000 - 0x4fffffff - PCI Memory
	45	* 0x50000000 - 0x50ffffff - PCI IO Space
	46	*/
b66a9383 RJ	47	#define CONFIG_PCI
	48
	49	#if defined(CONFIG_PCI)
96e48cf6 WD	50	#define CONFIG_PCI_PNP 1
96e48cf6 WD	51	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	52	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
96e48cf6 WD	53
	54	#define CONFIG_PCI_MEM_BUS 0x40000000
	55	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	56	#define CONFIG_PCI_MEM_SIZE 0x10000000
	57
	58	#define CONFIG_PCI_IO_BUS 0x50000000
	59	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	60	#define CONFIG_PCI_IO_SIZE 0x01000000
b66a9383	61	#endif
96e48cf6	62
6d0f6bcf	63	#define CONFIG_SYS_XLB_PIPELINING 1
e1599e83	64
63ff004c	65	#define CONFIG_MII 1
96e48cf6	66	#define CONFIG_EEPRO100 1
6d0f6bcf	67	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
f54ebdfa	68	#define CONFIG_NS8382X 1
96e48cf6	69
132ba5fd WD	70	/* Partitions */
	71	#define CONFIG_MAC_PARTITION
	72	#define CONFIG_DOS_PARTITION
64f70bed	73	#define CONFIG_ISO_PARTITION
132ba5fd	74
80885a9d	75	/* USB */
ae3b770e	76	#define CONFIG_USB_OHCI_NEW
80885a9d	77	#define CONFIG_USB_STORAGE
6d0f6bcf JCPV	78	#define CONFIG_SYS_OHCI_BE_CONTROLLER
	79	#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
	80	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	81	#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
	82	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
	83	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
ae3b770e	84
414eec35 WD	85	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
414eec35 WD	86
348f258f	87
945af8d7	88	/*
11799434	89	* BOOTP options
945af8d7	90	*/
11799434 JL	91	#define CONFIG_BOOTP_BOOTFILESIZE
	92	#define CONFIG_BOOTP_BOOTPATH
	93	#define CONFIG_BOOTP_GATEWAY
	94	#define CONFIG_BOOTP_HOSTNAME
	95
	96
945af8d7	97	/*
348f258f	98	* Command line configuration.
945af8d7	99	*/
348f258f JL	100	#include <config_cmd_default.h>
	101
	102	#define CONFIG_CMD_EEPROM
	103	#define CONFIG_CMD_FAT
	104	#define CONFIG_CMD_I2C
	105	#define CONFIG_CMD_IDE
	106	#define CONFIG_CMD_NFS
	107	#define CONFIG_CMD_SNTP
11799434 JL	108	#define CONFIG_CMD_USB
	109
	110	#if defined(CONFIG_PCI)
	111	#define CONFIG_CMD_PCI
	112	#endif
348f258f	113
945af8d7	114
14d0a02a	115	#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
6d0f6bcf JCPV	116	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	117	# define CONFIG_SYS_LOWBOOT16 1
5cf9da48	118	#endif
14d0a02a	119	#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
09e4b0c5	120	#if defined(CONFIG_LITE5200B)
6d0f6bcf	121	# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
09e4b0c5	122	#else
6d0f6bcf JCPV	123	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	124	# define CONFIG_SYS_LOWBOOT08 1
5cf9da48	125	#endif
09e4b0c5	126	#endif
5cf9da48	127
945af8d7 WD	128	/*
	129	* Autobooting
	130	*/
	131	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
5cf9da48 WD	132
5cf9da48 WD	133	#define CONFIG_PREBOOT "echo;" \
32bf3d14	134	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
5cf9da48 WD	135	"echo"
	136
	137	#undef CONFIG_BOOTARGS
	138
	139	#define CONFIG_EXTRA_ENV_SETTINGS \
	140	"netdev=eth0\0" \
	141	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	142	"nfsroot=${serverip}:${rootpath}\0" \
5cf9da48	143	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	144	"addip=setenv bootargs ${bootargs} " \
	145	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	146	":${hostname}:${netdev}:off panic=1\0" \
5cf9da48	147	"flash_nfs=run nfsargs addip;" \
fe126d8b	148	"bootm ${kernel_addr}\0" \
5cf9da48	149	"flash_self=run ramargs addip;" \
fe126d8b WD	150	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	151	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
5cf9da48 WD	152	"rootpath=/opt/eldk/ppc_82xx\0" \
	153	"bootfile=/tftpboot/MPC5200/uImage\0" \
	154	""
	155
	156	#define CONFIG_BOOTCOMMAND "run flash_self"
945af8d7	157
acf98e7f WD	158	/*
	159	* IPB Bus clocking configuration.
	160	*/
09e4b0c5	161	#if defined(CONFIG_LITE5200B)
6d0f6bcf	162	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
09e4b0c5	163	#else
6d0f6bcf	164	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
acf98e7f	165	#endif
e59581c5 SR	166
e59581c5 SR	167	/* pass open firmware flat tree */
cf2817a8	168	#define CONFIG_OF_LIBFDT 1
e59581c5 SR	169	#define CONFIG_OF_BOARD_SETUP 1
e59581c5 SR	170
e59581c5 SR	171	#define OF_CPU "PowerPC,5200@0"
e59581c5 SR	172	#define OF_SOC "soc5200@f0000000"
39f23cd9	173	#define OF_TBCLK (bd->bi_busfreq / 4)
e59581c5 SR	174	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
e59581c5 SR	175
945af8d7 WD	176	/*
	177	* I2C configuration
	178	*/
531716e1	179	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	180	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
ab209d51	181
6d0f6bcf JCPV	182	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	183	#define CONFIG_SYS_I2C_SLAVE 0x7F
531716e1 WD	184
	185	/*
	186	* EEPROM configuration
	187	*/
6d0f6bcf JCPV	188	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	189	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	190	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	191	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
945af8d7 WD	192
	193	/*
	194	* Flash configuration
	195	*/
09e4b0c5	196	#if defined(CONFIG_LITE5200B)
6d0f6bcf JCPV	197	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	198	#define CONFIG_SYS_FLASH_SIZE 0x01000000
	199	#if !defined(CONFIG_SYS_LOWBOOT)
	200	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
	201	#else /* CONFIG_SYS_LOWBOOT */
	202	#if defined(CONFIG_SYS_LOWBOOT08)
	203	# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
09e4b0c5	204	#endif
6d0f6bcf JCPV	205	#if defined(CONFIG_SYS_LOWBOOT16)
6d0f6bcf JCPV	206	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
09e4b0c5	207	#endif
6d0f6bcf	208	#endif /* CONFIG_SYS_LOWBOOT */
09e4b0c5	209	#else /* !CONFIG_LITE5200B (IceCube)*/
6d0f6bcf JCPV	210	#define CONFIG_SYS_FLASH_BASE 0xFF000000
	211	#define CONFIG_SYS_FLASH_SIZE 0x01000000
	212	#if !defined(CONFIG_SYS_LOWBOOT)
	213	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
	214	#else /* CONFIG_SYS_LOWBOOT */
	215	#if defined(CONFIG_SYS_LOWBOOT08)
	216	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
5cf9da48	217	#endif
6d0f6bcf JCPV	218	#if defined(CONFIG_SYS_LOWBOOT16)
6d0f6bcf JCPV	219	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
7152b1d0	220	#endif
6d0f6bcf	221	#endif /* CONFIG_SYS_LOWBOOT */
09e4b0c5	222	#endif /* CONFIG_LITE5200B */
6d0f6bcf	223	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
7152b1d0	224
6d0f6bcf	225	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
945af8d7	226
6d0f6bcf JCPV	227	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	228	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
945af8d7	229
96e48cf6	230	#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
945af8d7	231
09e4b0c5	232	#if defined(CONFIG_LITE5200B)
00b1883a	233	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	234	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	235	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
09e4b0c5 WD	236	#endif
09e4b0c5 WD	237
945af8d7 WD	238
	239	/*
	240	* Environment settings
	241	*/
5a1aceb0	242	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	243	#define CONFIG_ENV_SIZE 0x10000
09e4b0c5	244	#if defined(CONFIG_LITE5200B)
0e8d1586	245	#define CONFIG_ENV_SECT_SIZE 0x20000
09e4b0c5	246	#else
0e8d1586	247	#define CONFIG_ENV_SECT_SIZE 0x10000
09e4b0c5	248	#endif
96e48cf6	249	#define CONFIG_ENV_OVERWRITE 1
945af8d7 WD	250
	251	/*
	252	* Memory map
	253	*/
6d0f6bcf JCPV	254	#define CONFIG_SYS_MBAR 0xF0000000
	255	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	256	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
945af8d7 WD	257
945af8d7 WD	258	/* Use SRAM until RAM will be available */
6d0f6bcf	259	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	260	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
945af8d7 WD	261
945af8d7 WD	262
25ddd1fb	263	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	264	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
945af8d7	265
14d0a02a	266	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	267	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	268	# define CONFIG_SYS_RAMBOOT 1
945af8d7 WD	269	#endif
945af8d7 WD	270
6d0f6bcf	271	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
d2e22731	272	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
6d0f6bcf	273	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
945af8d7 WD	274
	275	/*
	276	* Ethernet configuration
	277	*/
cbd8a35c	278	#define CONFIG_MPC5xxx_FEC 1
86321fc1	279	#define CONFIG_MPC5xxx_FEC_MII100
04a85b3b	280	/*
86321fc1	281	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
7e780369	282	*/
86321fc1	283	/* #define CONFIG_MPC5xxx_FEC_MII10 */
d4ca31c4	284	#define CONFIG_PHY_ADDR 0x00
945af8d7 WD	285
	286	/*
	287	* GPIO configuration
	288	*/
b2001f27	289	#ifdef CONFIG_MPC5200_DDR
6d0f6bcf	290	#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004
b2001f27	291	#else
6d0f6bcf	292	#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
b2001f27	293	#endif
945af8d7 WD	294
	295	/*
	296	* Miscellaneous configurable options
	297	*/
6d0f6bcf	298	#define CONFIG_SYS_LONGHELP /* undef to save memory */
348f258f	299	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	300	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
945af8d7	301	#else
6d0f6bcf	302	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
945af8d7	303	#endif
6d0f6bcf JCPV	304	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	305	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	306	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
945af8d7	307
d2e22731 WD	308	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
d2e22731 WD	309	#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
d2e22731	310
6d0f6bcf JCPV	311	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	312	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
945af8d7	313
6d0f6bcf	314	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
945af8d7	315
6d0f6bcf	316	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
348f258f	317	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	318	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
348f258f JL	319	#endif
348f258f JL	320
945af8d7 WD	321	/*
	322	* Various low-level settings
	323	*/
6d0f6bcf JCPV	324	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	325	#define CONFIG_SYS_HID0_FINAL HID0_ICE
945af8d7	326
09e4b0c5	327	#if defined(CONFIG_LITE5200B)
6d0f6bcf JCPV	328	#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
	329	#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
	330	#define CONFIG_SYS_CS1_CFG 0x00047800
	331	#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
	332	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	333	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
	334	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	335	#define CONFIG_SYS_BOOTCS_CFG 0x00047800
09e4b0c5	336	#else /* IceCube aka Lite5200 */
b2001f27 WD	337	#ifdef CONFIG_MPC5200_DDR
b2001f27 WD	338
6d0f6bcf JCPV	339	#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
	340	#define CONFIG_SYS_BOOTCS_SIZE 0x00800000
	341	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	342	#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
	343	#define CONFIG_SYS_CS1_SIZE 0x00800000
	344	#define CONFIG_SYS_CS1_CFG 0x00047800
b2001f27 WD	345
	346	#else /* !CONFIG_MPC5200_DDR */
	347
6d0f6bcf JCPV	348	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	349	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	350	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	351	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	352	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
945af8d7	353
b2001f27	354	#endif /* CONFIG_MPC5200_DDR */
09e4b0c5	355	#endif /CONFIG_LITE5200B /
b2001f27	356
6d0f6bcf JCPV	357	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	358	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
945af8d7	359
6d0f6bcf	360	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
c3f9d493 WD	361
	362	/*-----------------------------------------------------------------------
	363	* USB stuff
	364	*-----------------------------------------------------------------------
	365	*/
4d13cbad WD	366	#define CONFIG_USB_CLOCK 0x0001BBBB
4d13cbad WD	367	#define CONFIG_USB_CONFIG 0x00001000
945af8d7	368
132ba5fd WD	369	/*-----------------------------------------------------------------------
	370	* IDE/ATA stuff Supports IDE harddisk
	371	*-----------------------------------------------------------------------
	372	*/
	373
	374	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	375
	376	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	377	#undef CONFIG_IDE_LED /* LED for ide not supported */
	378
	379	#define CONFIG_IDE_RESET /* reset for ide supported */
	380	#define CONFIG_IDE_PREINIT
	381
6d0f6bcf JCPV	382	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	383	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
132ba5fd	384
6d0f6bcf	385	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
132ba5fd	386
6d0f6bcf	387	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
132ba5fd WD	388
132ba5fd WD	389	/* Offset for data I/O */
6d0f6bcf	390	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
132ba5fd WD	391
132ba5fd WD	392	/* Offset for normal register accesses */
6d0f6bcf	393	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
132ba5fd WD	394
132ba5fd WD	395	/* Offset for alternate registers */
6d0f6bcf	396	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
132ba5fd WD	397
132ba5fd WD	398	/* Interval between registers */
6d0f6bcf	399	#define CONFIG_SYS_ATA_STRIDE 4
132ba5fd	400
64f70bed WD	401	#define CONFIG_ATAPI 1
64f70bed WD	402
945af8d7	403	#endif /* __CONFIG_H */