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945af8d7 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2003-2005 |
945af8d7 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | ||
cbd8a35c | 32 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
fd428c05 | 33 | #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ |
945af8d7 WD |
34 | #define CONFIG_ICECUBE 1 /* ... on IceCube board */ |
35 | ||
2ae18241 WD |
36 | /* |
37 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
38 | * 0xFFF00000 boot high (standard configuration) | |
39 | * 0xFF000000 boot low for 16 MiB boards | |
40 | * 0xFF800000 boot low for 8 MiB boards | |
41 | * 0x00100000 boot from RAM (for testing only) | |
42 | */ | |
43 | #ifndef CONFIG_SYS_TEXT_BASE | |
44 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
45 | #endif | |
46 | ||
6d0f6bcf | 47 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
945af8d7 | 48 | |
31d82672 BB |
49 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
50 | ||
945af8d7 WD |
51 | /* |
52 | * Serial console configuration | |
53 | */ | |
54 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
55 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 56 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
945af8d7 | 57 | |
96e48cf6 | 58 | |
96e48cf6 WD |
59 | /* |
60 | * PCI Mapping: | |
61 | * 0x40000000 - 0x4fffffff - PCI Memory | |
62 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
63 | */ | |
b66a9383 RJ |
64 | #define CONFIG_PCI |
65 | ||
66 | #if defined(CONFIG_PCI) | |
96e48cf6 WD |
67 | #define CONFIG_PCI_PNP 1 |
68 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 69 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
96e48cf6 WD |
70 | |
71 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
72 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
73 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
74 | ||
75 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
76 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
77 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
b66a9383 | 78 | #endif |
96e48cf6 | 79 | |
6d0f6bcf | 80 | #define CONFIG_SYS_XLB_PIPELINING 1 |
e1599e83 | 81 | |
63ff004c | 82 | #define CONFIG_MII 1 |
96e48cf6 | 83 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 84 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
f54ebdfa | 85 | #define CONFIG_NS8382X 1 |
96e48cf6 | 86 | |
132ba5fd WD |
87 | /* Partitions */ |
88 | #define CONFIG_MAC_PARTITION | |
89 | #define CONFIG_DOS_PARTITION | |
64f70bed | 90 | #define CONFIG_ISO_PARTITION |
132ba5fd | 91 | |
80885a9d | 92 | /* USB */ |
ae3b770e | 93 | #define CONFIG_USB_OHCI_NEW |
80885a9d | 94 | #define CONFIG_USB_STORAGE |
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
96 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT | |
97 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
98 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
99 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
100 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
ae3b770e | 101 | |
414eec35 WD |
102 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
103 | ||
348f258f | 104 | |
945af8d7 | 105 | /* |
11799434 | 106 | * BOOTP options |
945af8d7 | 107 | */ |
11799434 JL |
108 | #define CONFIG_BOOTP_BOOTFILESIZE |
109 | #define CONFIG_BOOTP_BOOTPATH | |
110 | #define CONFIG_BOOTP_GATEWAY | |
111 | #define CONFIG_BOOTP_HOSTNAME | |
112 | ||
113 | ||
945af8d7 | 114 | /* |
348f258f | 115 | * Command line configuration. |
945af8d7 | 116 | */ |
348f258f JL |
117 | #include <config_cmd_default.h> |
118 | ||
119 | #define CONFIG_CMD_EEPROM | |
120 | #define CONFIG_CMD_FAT | |
121 | #define CONFIG_CMD_I2C | |
122 | #define CONFIG_CMD_IDE | |
123 | #define CONFIG_CMD_NFS | |
124 | #define CONFIG_CMD_SNTP | |
11799434 JL |
125 | #define CONFIG_CMD_USB |
126 | ||
127 | #if defined(CONFIG_PCI) | |
128 | #define CONFIG_CMD_PCI | |
129 | #endif | |
348f258f | 130 | |
945af8d7 | 131 | |
14d0a02a | 132 | #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ |
6d0f6bcf JCPV |
133 | # define CONFIG_SYS_LOWBOOT 1 |
134 | # define CONFIG_SYS_LOWBOOT16 1 | |
5cf9da48 | 135 | #endif |
14d0a02a | 136 | #if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ |
09e4b0c5 | 137 | #if defined(CONFIG_LITE5200B) |
6d0f6bcf | 138 | # error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B |
09e4b0c5 | 139 | #else |
6d0f6bcf JCPV |
140 | # define CONFIG_SYS_LOWBOOT 1 |
141 | # define CONFIG_SYS_LOWBOOT08 1 | |
5cf9da48 | 142 | #endif |
09e4b0c5 | 143 | #endif |
5cf9da48 | 144 | |
945af8d7 WD |
145 | /* |
146 | * Autobooting | |
147 | */ | |
148 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
5cf9da48 WD |
149 | |
150 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 151 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
5cf9da48 WD |
152 | "echo" |
153 | ||
154 | #undef CONFIG_BOOTARGS | |
155 | ||
156 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
157 | "netdev=eth0\0" \ | |
158 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 159 | "nfsroot=${serverip}:${rootpath}\0" \ |
5cf9da48 | 160 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
161 | "addip=setenv bootargs ${bootargs} " \ |
162 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
163 | ":${hostname}:${netdev}:off panic=1\0" \ | |
5cf9da48 | 164 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 165 | "bootm ${kernel_addr}\0" \ |
5cf9da48 | 166 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
167 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
168 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
5cf9da48 WD |
169 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
170 | "bootfile=/tftpboot/MPC5200/uImage\0" \ | |
171 | "" | |
172 | ||
173 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
945af8d7 | 174 | |
acf98e7f WD |
175 | /* |
176 | * IPB Bus clocking configuration. | |
177 | */ | |
09e4b0c5 | 178 | #if defined(CONFIG_LITE5200B) |
6d0f6bcf | 179 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
09e4b0c5 | 180 | #else |
6d0f6bcf | 181 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
acf98e7f | 182 | #endif |
e59581c5 SR |
183 | |
184 | /* pass open firmware flat tree */ | |
cf2817a8 | 185 | #define CONFIG_OF_LIBFDT 1 |
e59581c5 SR |
186 | #define CONFIG_OF_BOARD_SETUP 1 |
187 | ||
e59581c5 SR |
188 | #define OF_CPU "PowerPC,5200@0" |
189 | #define OF_SOC "soc5200@f0000000" | |
39f23cd9 | 190 | #define OF_TBCLK (bd->bi_busfreq / 4) |
e59581c5 SR |
191 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" |
192 | ||
945af8d7 WD |
193 | /* |
194 | * I2C configuration | |
195 | */ | |
531716e1 | 196 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
6d0f6bcf | 197 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
ab209d51 | 198 | |
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
200 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
531716e1 WD |
201 | |
202 | /* | |
203 | * EEPROM configuration | |
204 | */ | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
206 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
207 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
208 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
945af8d7 WD |
209 | |
210 | /* | |
211 | * Flash configuration | |
212 | */ | |
09e4b0c5 | 213 | #if defined(CONFIG_LITE5200B) |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
215 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
216 | #if !defined(CONFIG_SYS_LOWBOOT) | |
217 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000) | |
218 | #else /* CONFIG_SYS_LOWBOOT */ | |
219 | #if defined(CONFIG_SYS_LOWBOOT08) | |
220 | # error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B | |
09e4b0c5 | 221 | #endif |
6d0f6bcf JCPV |
222 | #if defined(CONFIG_SYS_LOWBOOT16) |
223 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000) | |
09e4b0c5 | 224 | #endif |
6d0f6bcf | 225 | #endif /* CONFIG_SYS_LOWBOOT */ |
09e4b0c5 | 226 | #else /* !CONFIG_LITE5200B (IceCube)*/ |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
228 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
229 | #if !defined(CONFIG_SYS_LOWBOOT) | |
230 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000) | |
231 | #else /* CONFIG_SYS_LOWBOOT */ | |
232 | #if defined(CONFIG_SYS_LOWBOOT08) | |
233 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000) | |
5cf9da48 | 234 | #endif |
6d0f6bcf JCPV |
235 | #if defined(CONFIG_SYS_LOWBOOT16) |
236 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) | |
7152b1d0 | 237 | #endif |
6d0f6bcf | 238 | #endif /* CONFIG_SYS_LOWBOOT */ |
09e4b0c5 | 239 | #endif /* CONFIG_LITE5200B */ |
6d0f6bcf | 240 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ |
7152b1d0 | 241 | |
6d0f6bcf | 242 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
945af8d7 | 243 | |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
245 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
945af8d7 | 246 | |
96e48cf6 | 247 | #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ |
945af8d7 | 248 | |
09e4b0c5 | 249 | #if defined(CONFIG_LITE5200B) |
00b1883a | 250 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_FLASH_CFI |
252 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START} | |
09e4b0c5 WD |
253 | #endif |
254 | ||
945af8d7 WD |
255 | |
256 | /* | |
257 | * Environment settings | |
258 | */ | |
5a1aceb0 | 259 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 260 | #define CONFIG_ENV_SIZE 0x10000 |
09e4b0c5 | 261 | #if defined(CONFIG_LITE5200B) |
0e8d1586 | 262 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
09e4b0c5 | 263 | #else |
0e8d1586 | 264 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
09e4b0c5 | 265 | #endif |
96e48cf6 | 266 | #define CONFIG_ENV_OVERWRITE 1 |
945af8d7 WD |
267 | |
268 | /* | |
269 | * Memory map | |
270 | */ | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_MBAR 0xF0000000 |
272 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
273 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
945af8d7 WD |
274 | |
275 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 276 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 277 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
945af8d7 WD |
278 | |
279 | ||
25ddd1fb | 280 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 281 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
945af8d7 | 282 | |
14d0a02a | 283 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
284 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
285 | # define CONFIG_SYS_RAMBOOT 1 | |
945af8d7 WD |
286 | #endif |
287 | ||
6d0f6bcf | 288 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
d2e22731 | 289 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ |
6d0f6bcf | 290 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
945af8d7 WD |
291 | |
292 | /* | |
293 | * Ethernet configuration | |
294 | */ | |
cbd8a35c | 295 | #define CONFIG_MPC5xxx_FEC 1 |
86321fc1 | 296 | #define CONFIG_MPC5xxx_FEC_MII100 |
04a85b3b | 297 | /* |
86321fc1 | 298 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
7e780369 | 299 | */ |
86321fc1 | 300 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
d4ca31c4 | 301 | #define CONFIG_PHY_ADDR 0x00 |
945af8d7 WD |
302 | |
303 | /* | |
304 | * GPIO configuration | |
305 | */ | |
b2001f27 | 306 | #ifdef CONFIG_MPC5200_DDR |
6d0f6bcf | 307 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004 |
b2001f27 | 308 | #else |
6d0f6bcf | 309 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 |
b2001f27 | 310 | #endif |
945af8d7 WD |
311 | |
312 | /* | |
313 | * Miscellaneous configurable options | |
314 | */ | |
6d0f6bcf JCPV |
315 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
316 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
348f258f | 317 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 318 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
945af8d7 | 319 | #else |
6d0f6bcf | 320 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
945af8d7 | 321 | #endif |
6d0f6bcf JCPV |
322 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
323 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
324 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
945af8d7 | 325 | |
d2e22731 WD |
326 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
327 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ | |
d2e22731 | 328 | |
6d0f6bcf JCPV |
329 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
330 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
945af8d7 | 331 | |
6d0f6bcf | 332 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
945af8d7 | 333 | |
6d0f6bcf | 334 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
945af8d7 | 335 | |
6d0f6bcf | 336 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
348f258f | 337 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 338 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
348f258f JL |
339 | #endif |
340 | ||
945af8d7 WD |
341 | /* |
342 | * Various low-level settings | |
343 | */ | |
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
345 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
945af8d7 | 346 | |
09e4b0c5 | 347 | #if defined(CONFIG_LITE5200B) |
6d0f6bcf JCPV |
348 | #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE |
349 | #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE | |
350 | #define CONFIG_SYS_CS1_CFG 0x00047800 | |
351 | #define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE) | |
352 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
353 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START | |
354 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
355 | #define CONFIG_SYS_BOOTCS_CFG 0x00047800 | |
09e4b0c5 | 356 | #else /* IceCube aka Lite5200 */ |
b2001f27 WD |
357 | #ifdef CONFIG_MPC5200_DDR |
358 | ||
6d0f6bcf JCPV |
359 | #define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE) |
360 | #define CONFIG_SYS_BOOTCS_SIZE 0x00800000 | |
361 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 | |
362 | #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE | |
363 | #define CONFIG_SYS_CS1_SIZE 0x00800000 | |
364 | #define CONFIG_SYS_CS1_CFG 0x00047800 | |
b2001f27 WD |
365 | |
366 | #else /* !CONFIG_MPC5200_DDR */ | |
367 | ||
6d0f6bcf JCPV |
368 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
369 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
370 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 | |
371 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
372 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
945af8d7 | 373 | |
b2001f27 | 374 | #endif /* CONFIG_MPC5200_DDR */ |
09e4b0c5 | 375 | #endif /*CONFIG_LITE5200B */ |
b2001f27 | 376 | |
6d0f6bcf JCPV |
377 | #define CONFIG_SYS_CS_BURST 0x00000000 |
378 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
945af8d7 | 379 | |
6d0f6bcf | 380 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
c3f9d493 WD |
381 | |
382 | /*----------------------------------------------------------------------- | |
383 | * USB stuff | |
384 | *----------------------------------------------------------------------- | |
385 | */ | |
4d13cbad WD |
386 | #define CONFIG_USB_CLOCK 0x0001BBBB |
387 | #define CONFIG_USB_CONFIG 0x00001000 | |
945af8d7 | 388 | |
132ba5fd WD |
389 | /*----------------------------------------------------------------------- |
390 | * IDE/ATA stuff Supports IDE harddisk | |
391 | *----------------------------------------------------------------------- | |
392 | */ | |
393 | ||
394 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
395 | ||
396 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
397 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
398 | ||
399 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
400 | #define CONFIG_IDE_PREINIT | |
401 | ||
6d0f6bcf JCPV |
402 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
403 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ | |
132ba5fd | 404 | |
6d0f6bcf | 405 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
132ba5fd | 406 | |
6d0f6bcf | 407 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
132ba5fd WD |
408 | |
409 | /* Offset for data I/O */ | |
6d0f6bcf | 410 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
132ba5fd WD |
411 | |
412 | /* Offset for normal register accesses */ | |
6d0f6bcf | 413 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
132ba5fd WD |
414 | |
415 | /* Offset for alternate registers */ | |
6d0f6bcf | 416 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
132ba5fd WD |
417 | |
418 | /* Interval between registers */ | |
6d0f6bcf | 419 | #define CONFIG_SYS_ATA_STRIDE 4 |
132ba5fd | 420 | |
64f70bed WD |
421 | #define CONFIG_ATAPI 1 |
422 | ||
945af8d7 | 423 | #endif /* __CONFIG_H */ |