[people/ms/u-boot.git] / include / configs / IceCube.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_ICECUBE		1	/* ... on IceCube board */

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI

#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000
#endif

#define CFG_XLB_PIPELINING	1

#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

#else
#define CONFIG_MII		1
#endif

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CFG_OHCI_BE_CONTROLLER
#undef CFG_USB_OHCI_BOARD_INIT
#define CFG_USB_OHCI_CPU_INIT	1
#define CFG_USB_OHCI_REGS_BASE	MPC5XXX_USB
#define CFG_USB_OHCI_SLOT_NAME	"mpc5200"
#define CFG_USB_OHCI_MAX_ROOT_PORTS	15

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif


#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
#   define CFG_LOWBOOT	        1
#   define CFG_LOWBOOT16	1
#endif
#if (TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
#if defined(CONFIG_LITE5200B)
#   error CFG_LOWBOOT08 is incompatible with the Lite5200B
#else
#   define CFG_LOWBOOT	        1
#   define CFG_LOWBOOT08	1
#endif
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

#if defined(CONFIG_MPC5200)
/*
 * IPB Bus clocking configuration.
 */
#if defined(CONFIG_LITE5200B)
#define CFG_IPBCLK_EQUALS_XLBCLK 	/* define for 133MHz speed */
#else
#undef CFG_IPBCLK_EQUALS_XLBCLK   	/* define for 133MHz speed */
#endif
#endif /* CONFIG_MPC5200 */

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN		1
#define CFG_EEPROM_PAGE_WRITE_BITS	3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * Flash configuration
 */
#if defined(CONFIG_LITE5200B)
#define CFG_FLASH_BASE		0xFE000000
#define CFG_FLASH_SIZE		0x01000000
#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x01760000 + 0x00800000)
#else	/* CFG_LOWBOOT */
#if defined(CFG_LOWBOOT08)
# error CFG_LOWBOOT08 is incompatible with the Lite5200B
#endif
#if defined(CFG_LOWBOOT16)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x01060000)
#endif
#endif /* CFG_LOWBOOT */
#else /* !CONFIG_LITE5200B (IceCube)*/
#define CFG_FLASH_BASE		0xFF000000
#define CFG_FLASH_SIZE		0x01000000
#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00740000 + 0x00800000)
#else	/* CFG_LOWBOOT */
#if defined(CFG_LOWBOOT08)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000 + 0x00800000)
#endif
#if defined(CFG_LOWBOOT16)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
#endif
#endif	/* CFG_LOWBOOT */
#endif /* CONFIG_LITE5200B */
#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks      */

#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */

#if defined(CONFIG_LITE5200B)
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_BANKS_LIST	{CFG_CS1_START,CFG_CS0_START}
#endif


/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x10000
#if defined(CONFIG_LITE5200B)
#define CFG_ENV_SECT_SIZE	0x20000
#else
#define CFG_ENV_SECT_SIZE	0x10000
#endif
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00
#if defined(CONFIG_LITE5200B)
#define CONFIG_FEC_MII100	1
#endif

/*
 * GPIO configuration
 */
#ifdef CONFIG_MPC5200_DDR
#define CFG_GPS_PORT_CONFIG	0x90000004
#else
#define CFG_GPS_PORT_CONFIG	0x10000004
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#if defined(CONFIG_LITE5200B)
#define CFG_CS1_START		CFG_FLASH_BASE
#define CFG_CS1_SIZE		CFG_FLASH_SIZE
#define CFG_CS1_CFG		0x00047800
#define CFG_CS0_START		(CFG_FLASH_BASE + CFG_FLASH_SIZE)
#define CFG_CS0_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_START	CFG_CS0_START
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x00047800
#else /* IceCube aka Lite5200 */
#ifdef CONFIG_MPC5200_DDR

#define CFG_BOOTCS_START	(CFG_CS1_START + CFG_CS1_SIZE)
#define CFG_BOOTCS_SIZE		0x00800000
#define CFG_BOOTCS_CFG		0x00047801
#define CFG_CS1_START		CFG_FLASH_BASE
#define CFG_CS1_SIZE		0x00800000
#define CFG_CS1_CFG		0x00047800

#else /* !CONFIG_MPC5200_DDR */

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x00047801
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

#endif /* CONFIG_MPC5200_DDR */
#endif /*CONFIG_LITE5200B */

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CFG_ATA_STRIDE          4

#define CONFIG_ATAPI            1

#endif /* __CONFIG_H */
Commit	Line	Data
945af8d7	1	/*
414eec35	2	* (C) Copyright 2003-2005
945af8d7 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
cbd8a35c	32	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
945af8d7 WD	33	#define CONFIG_ICECUBE 1 /* ... on IceCube board */
945af8d7 WD	34
b2001f27	35	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
945af8d7 WD	36
	37	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	38	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	39
945af8d7 WD	40	/*
	41	* Serial console configuration
	42	*/
	43	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	44	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	45	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	46
96e48cf6 WD	47
	48	#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
	49	/*
	50	* PCI Mapping:
	51	* 0x40000000 - 0x4fffffff - PCI Memory
	52	* 0x50000000 - 0x50ffffff - PCI IO Space
	53	*/
b66a9383 RJ	54	#define CONFIG_PCI
	55
	56	#if defined(CONFIG_PCI)
96e48cf6 WD	57	#define CONFIG_PCI_PNP 1
	58	#define CONFIG_PCI_SCAN_SHOW 1
	59
	60	#define CONFIG_PCI_MEM_BUS 0x40000000
	61	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	62	#define CONFIG_PCI_MEM_SIZE 0x10000000
	63
	64	#define CONFIG_PCI_IO_BUS 0x50000000
	65	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	66	#define CONFIG_PCI_IO_SIZE 0x01000000
b66a9383	67	#endif
96e48cf6	68
e1599e83 WD	69	#define CFG_XLB_PIPELINING 1
e1599e83 WD	70
96e48cf6	71	#define CONFIG_NET_MULTI 1
63ff004c	72	#define CONFIG_MII 1
96e48cf6 WD	73	#define CONFIG_EEPRO100 1
96e48cf6 WD	74	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
f54ebdfa	75	#define CONFIG_NS8382X 1
96e48cf6	76
11799434	77	#else
63ff004c	78	#define CONFIG_MII 1
96e48cf6 WD	79	#endif
96e48cf6 WD	80
132ba5fd WD	81	/* Partitions */
	82	#define CONFIG_MAC_PARTITION
	83	#define CONFIG_DOS_PARTITION
64f70bed	84	#define CONFIG_ISO_PARTITION
132ba5fd	85
80885a9d	86	/* USB */
ae3b770e	87	#define CONFIG_USB_OHCI_NEW
80885a9d	88	#define CONFIG_USB_STORAGE
72657570	89	#define CFG_OHCI_BE_CONTROLLER
ae3b770e	90	#undef CFG_USB_OHCI_BOARD_INIT
72657570	91	#define CFG_USB_OHCI_CPU_INIT 1
ae3b770e MK	92	#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB
	93	#define CFG_USB_OHCI_SLOT_NAME "mpc5200"
	94	#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
	95
414eec35 WD	96	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
414eec35 WD	97
348f258f	98
945af8d7	99	/*
11799434	100	* BOOTP options
945af8d7	101	*/
11799434 JL	102	#define CONFIG_BOOTP_BOOTFILESIZE
	103	#define CONFIG_BOOTP_BOOTPATH
	104	#define CONFIG_BOOTP_GATEWAY
	105	#define CONFIG_BOOTP_HOSTNAME
	106
	107
945af8d7	108	/*
348f258f	109	* Command line configuration.
945af8d7	110	*/
348f258f JL	111	#include <config_cmd_default.h>
	112
	113	#define CONFIG_CMD_EEPROM
	114	#define CONFIG_CMD_FAT
	115	#define CONFIG_CMD_I2C
	116	#define CONFIG_CMD_IDE
	117	#define CONFIG_CMD_NFS
	118	#define CONFIG_CMD_SNTP
11799434 JL	119	#define CONFIG_CMD_USB
	120
	121	#if defined(CONFIG_PCI)
	122	#define CONFIG_CMD_PCI
	123	#endif
348f258f	124
945af8d7	125
5cf9da48 WD	126	#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
	127	# define CFG_LOWBOOT 1
	128	# define CFG_LOWBOOT16 1
	129	#endif
	130	#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
09e4b0c5 WD	131	#if defined(CONFIG_LITE5200B)
	132	# error CFG_LOWBOOT08 is incompatible with the Lite5200B
	133	#else
5cf9da48 WD	134	# define CFG_LOWBOOT 1
	135	# define CFG_LOWBOOT08 1
	136	#endif
09e4b0c5	137	#endif
5cf9da48	138
945af8d7 WD	139	/*
	140	* Autobooting
	141	*/
	142	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
5cf9da48 WD	143
	144	#define CONFIG_PREBOOT "echo;" \
	145	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	146	"echo"
	147
	148	#undef CONFIG_BOOTARGS
	149
	150	#define CONFIG_EXTRA_ENV_SETTINGS \
	151	"netdev=eth0\0" \
	152	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	153	"nfsroot=${serverip}:${rootpath}\0" \
5cf9da48	154	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	155	"addip=setenv bootargs ${bootargs} " \
	156	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	157	":${hostname}:${netdev}:off panic=1\0" \
5cf9da48	158	"flash_nfs=run nfsargs addip;" \
fe126d8b	159	"bootm ${kernel_addr}\0" \
5cf9da48	160	"flash_self=run ramargs addip;" \
fe126d8b WD	161	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	162	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
5cf9da48 WD	163	"rootpath=/opt/eldk/ppc_82xx\0" \
	164	"bootfile=/tftpboot/MPC5200/uImage\0" \
	165	""
	166
	167	#define CONFIG_BOOTCOMMAND "run flash_self"
945af8d7	168
acf98e7f WD	169	#if defined(CONFIG_MPC5200)
	170	/*
	171	* IPB Bus clocking configuration.
	172	*/
09e4b0c5	173	#if defined(CONFIG_LITE5200B)
c99512d6	174	#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
09e4b0c5	175	#else
c99512d6	176	#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
acf98e7f	177	#endif
09e4b0c5	178	#endif /* CONFIG_MPC5200 */
e59581c5 SR	179
e59581c5 SR	180	/* pass open firmware flat tree */
cf2817a8	181	#define CONFIG_OF_LIBFDT 1
e59581c5 SR	182	#define CONFIG_OF_BOARD_SETUP 1
e59581c5 SR	183
e59581c5 SR	184	#define OF_CPU "PowerPC,5200@0"
e59581c5 SR	185	#define OF_SOC "soc5200@f0000000"
39f23cd9	186	#define OF_TBCLK (bd->bi_busfreq / 4)
e59581c5 SR	187	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
e59581c5 SR	188
945af8d7 WD	189	/*
	190	* I2C configuration
	191	*/
531716e1	192	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
ab209d51	193	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	194
	195	#define CFG_I2C_SPEED 100000 /* 100 kHz */
531716e1 WD	196	#define CFG_I2C_SLAVE 0x7F
	197
	198	/*
	199	* EEPROM configuration
	200	*/
	201	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	202	#define CFG_I2C_EEPROM_ADDR_LEN 1
	203	#define CFG_EEPROM_PAGE_WRITE_BITS 3
ab209d51	204	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
945af8d7 WD	205
	206	/*
	207	* Flash configuration
	208	*/
09e4b0c5 WD	209	#if defined(CONFIG_LITE5200B)
	210	#define CFG_FLASH_BASE 0xFE000000
	211	#define CFG_FLASH_SIZE 0x01000000
	212	#if !defined(CFG_LOWBOOT)
	213	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01760000 + 0x00800000)
	214	#else /* CFG_LOWBOOT */
	215	#if defined(CFG_LOWBOOT08)
	216	# error CFG_LOWBOOT08 is incompatible with the Lite5200B
	217	#endif
	218	#if defined(CFG_LOWBOOT16)
	219	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01060000)
	220	#endif
	221	#endif /* CFG_LOWBOOT */
	222	#else /* !CONFIG_LITE5200B (IceCube)*/
4b248f3f	223	#define CFG_FLASH_BASE 0xFF000000
7152b1d0	224	#define CFG_FLASH_SIZE 0x01000000
5cf9da48	225	#if !defined(CFG_LOWBOOT)
4b248f3f	226	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
5cf9da48 WD	227	#else /* CFG_LOWBOOT */
5cf9da48 WD	228	#if defined(CFG_LOWBOOT08)
4b248f3f	229	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000)
5cf9da48 WD	230	#endif
5cf9da48 WD	231	#if defined(CFG_LOWBOOT16)
4b248f3f	232	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
7152b1d0	233	#endif
5cf9da48	234	#endif /* CFG_LOWBOOT */
09e4b0c5	235	#endif /* CONFIG_LITE5200B */
5cf9da48	236	#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
7152b1d0	237
945af8d7 WD	238	#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	239
	240	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	241	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	242
96e48cf6	243	#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
945af8d7	244
09e4b0c5 WD	245	#if defined(CONFIG_LITE5200B)
	246	#define CFG_FLASH_CFI_DRIVER
	247	#define CFG_FLASH_CFI
	248	#define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START}
	249	#endif
	250
945af8d7 WD	251
	252	/*
	253	* Environment settings
	254	*/
96e48cf6	255	#define CFG_ENV_IS_IN_FLASH 1
945af8d7	256	#define CFG_ENV_SIZE 0x10000
09e4b0c5 WD	257	#if defined(CONFIG_LITE5200B)
	258	#define CFG_ENV_SECT_SIZE 0x20000
	259	#else
96e48cf6	260	#define CFG_ENV_SECT_SIZE 0x10000
09e4b0c5	261	#endif
96e48cf6	262	#define CONFIG_ENV_OVERWRITE 1
945af8d7 WD	263
	264	/*
	265	* Memory map
	266	*/
4b248f3f	267	#define CFG_MBAR 0xF0000000
945af8d7	268	#define CFG_SDRAM_BASE 0x00000000
e0ac62d7	269	#define CFG_DEFAULT_MBAR 0x80000000
945af8d7 WD	270
	271	/* Use SRAM until RAM will be available */
	272	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	273	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	274
	275
	276	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	277	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	278	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	279
	280	#define CFG_MONITOR_BASE TEXT_BASE
	281	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
96e48cf6	282	# define CFG_RAMBOOT 1
945af8d7 WD	283	#endif
945af8d7 WD	284
af6d1dfc	285	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
945af8d7 WD	286	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	287	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	288
	289	/*
	290	* Ethernet configuration
	291	*/
cbd8a35c	292	#define CONFIG_MPC5xxx_FEC 1
04a85b3b	293	/*
7e780369 WD	294	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	295	*/
	296	/* #define CONFIG_FEC_10MBIT 1 */
d4ca31c4	297	#define CONFIG_PHY_ADDR 0x00
09e4b0c5 WD	298	#if defined(CONFIG_LITE5200B)
	299	#define CONFIG_FEC_MII100 1
	300	#endif
945af8d7 WD	301
	302	/*
	303	* GPIO configuration
	304	*/
b2001f27 WD	305	#ifdef CONFIG_MPC5200_DDR
	306	#define CFG_GPS_PORT_CONFIG 0x90000004
	307	#else
c3d98ed9	308	#define CFG_GPS_PORT_CONFIG 0x10000004
b2001f27	309	#endif
945af8d7 WD	310
	311	/*
	312	* Miscellaneous configurable options
	313	*/
	314	#define CFG_LONGHELP /* undef to save memory */
	315	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
348f258f	316	#if defined(CONFIG_CMD_KGDB)
945af8d7 WD	317	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	318	#else
	319	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	320	#endif
	321	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	322	#define CFG_MAXARGS 16 /* max number of command args */
	323	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	324
	325	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	326	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	327
	328	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	329
	330	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	331
348f258f JL	332	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	333	#if defined(CONFIG_CMD_KGDB)
	334	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	335	#endif
	336
945af8d7 WD	337	/*
	338	* Various low-level settings
	339	*/
b13fb01a	340	#if defined(CONFIG_MPC5200)
4f7cb08e WD	341	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
4f7cb08e WD	342	#define CFG_HID0_FINAL HID0_ICE
b13fb01a WD	343	#else
	344	#define CFG_HID0_INIT 0
	345	#define CFG_HID0_FINAL 0
	346	#endif
945af8d7	347
09e4b0c5 WD	348	#if defined(CONFIG_LITE5200B)
	349	#define CFG_CS1_START CFG_FLASH_BASE
	350	#define CFG_CS1_SIZE CFG_FLASH_SIZE
	351	#define CFG_CS1_CFG 0x00047800
	352	#define CFG_CS0_START (CFG_FLASH_BASE + CFG_FLASH_SIZE)
	353	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	354	#define CFG_BOOTCS_START CFG_CS0_START
	355	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	356	#define CFG_BOOTCS_CFG 0x00047800
	357	#else /* IceCube aka Lite5200 */
b2001f27 WD	358	#ifdef CONFIG_MPC5200_DDR
b2001f27 WD	359
7e780369	360	#define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE)
b2001f27 WD	361	#define CFG_BOOTCS_SIZE 0x00800000
b2001f27 WD	362	#define CFG_BOOTCS_CFG 0x00047801
7e780369	363	#define CFG_CS1_START CFG_FLASH_BASE
b2001f27 WD	364	#define CFG_CS1_SIZE 0x00800000
	365	#define CFG_CS1_CFG 0x00047800
	366
	367	#else /* !CONFIG_MPC5200_DDR */
	368
945af8d7 WD	369	#define CFG_BOOTCS_START CFG_FLASH_BASE
	370	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	371	#define CFG_BOOTCS_CFG 0x00047801
	372	#define CFG_CS0_START CFG_FLASH_BASE
	373	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	374
b2001f27	375	#endif /* CONFIG_MPC5200_DDR */
09e4b0c5	376	#endif /CONFIG_LITE5200B /
b2001f27	377
945af8d7 WD	378	#define CFG_CS_BURST 0x00000000
	379	#define CFG_CS_DEADCYCLE 0x33333333
	380
	381	#define CFG_RESET_ADDRESS 0xff000000
c3f9d493 WD	382
	383	/*-----------------------------------------------------------------------
	384	* USB stuff
	385	*-----------------------------------------------------------------------
	386	*/
4d13cbad WD	387	#define CONFIG_USB_CLOCK 0x0001BBBB
4d13cbad WD	388	#define CONFIG_USB_CONFIG 0x00001000
945af8d7	389
132ba5fd WD	390	/*-----------------------------------------------------------------------
	391	* IDE/ATA stuff Supports IDE harddisk
	392	*-----------------------------------------------------------------------
	393	*/
	394
	395	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	396
	397	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	398	#undef CONFIG_IDE_LED /* LED for ide not supported */
	399
	400	#define CONFIG_IDE_RESET /* reset for ide supported */
	401	#define CONFIG_IDE_PREINIT
	402
	403	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
64f70bed	404	#define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
132ba5fd WD	405
	406	#define CFG_ATA_IDE0_OFFSET 0x0000
	407
	408	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	409
	410	/* Offset for data I/O */
	411	#define CFG_ATA_DATA_OFFSET (0x0060)
	412
	413	/* Offset for normal register accesses */
	414	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	415
	416	/* Offset for alternate registers */
4b248f3f	417	#define CFG_ATA_ALT_OFFSET (0x005C)
132ba5fd WD	418
	419	/* Interval between registers */
	420	#define CFG_ATA_STRIDE 4
	421
64f70bed WD	422	#define CONFIG_ATAPI 1
64f70bed WD	423
945af8d7	424	#endif /* __CONFIG_H */