[people/ms/u-boot.git] / include / configs / IceCube.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU) */
#define CONFIG_ICECUBE		1	/* ... on IceCube board */

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI

#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000
#endif

#define CONFIG_SYS_XLB_PIPELINING	1

#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif


#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
#   define CONFIG_SYS_LOWBOOT	        1
#   define CONFIG_SYS_LOWBOOT16	1
#endif
#if (TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
#if defined(CONFIG_LITE5200B)
#   error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
#else
#   define CONFIG_SYS_LOWBOOT	        1
#   define CONFIG_SYS_LOWBOOT08	1
#endif
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
#else
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * Flash configuration
 */
#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
#else	/* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_SYS_LOWBOOT08)
# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
#endif
#if defined(CONFIG_SYS_LOWBOOT16)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x01060000)
#endif
#endif /* CONFIG_SYS_LOWBOOT */
#else /* !CONFIG_LITE5200B (IceCube)*/
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
#else	/* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_SYS_LOWBOOT08)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
#endif
#if defined(CONFIG_SYS_LOWBOOT16)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
#endif
#endif	/* CONFIG_SYS_LOWBOOT */
#endif /* CONFIG_LITE5200B */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks      */

#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */

#if defined(CONFIG_LITE5200B)
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
#endif


/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#if defined(CONFIG_LITE5200B)
#define CONFIG_ENV_SECT_SIZE	0x20000
#else
#define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 */
#ifdef CONFIG_MPC5200_DDR
#define CONFIG_SYS_GPS_PORT_CONFIG	0x90000004
#else
#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_CFG		0x00047800
#define CONFIG_SYS_CS0_START		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_CS0_START
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047800
#else /* IceCube aka Lite5200 */
#ifdef CONFIG_MPC5200_DDR

#define CONFIG_SYS_BOOTCS_START	(CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
#define CONFIG_SYS_BOOTCS_SIZE		0x00800000
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE		0x00800000
#define CONFIG_SYS_CS1_CFG		0x00047800

#else /* !CONFIG_MPC5200_DDR */

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#endif /* CONFIG_MPC5200_DDR */
#endif /*CONFIG_LITE5200B */

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#define CONFIG_ATAPI            1

#endif /* __CONFIG_H */
Commit	Line	Data
945af8d7	1	/*
414eec35	2	* (C) Copyright 2003-2005
945af8d7 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
cbd8a35c	32	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
fd428c05	33	#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
945af8d7 WD	34	#define CONFIG_ICECUBE 1 /* ... on IceCube board */
945af8d7 WD	35
6d0f6bcf	36	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
945af8d7 WD	37
	38	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	39	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	40
31d82672 BB	41	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	42
945af8d7 WD	43	/*
	44	* Serial console configuration
	45	*/
	46	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	47	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	48	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
945af8d7	49
96e48cf6	50
96e48cf6 WD	51	/*
	52	* PCI Mapping:
	53	* 0x40000000 - 0x4fffffff - PCI Memory
	54	* 0x50000000 - 0x50ffffff - PCI IO Space
	55	*/
b66a9383 RJ	56	#define CONFIG_PCI
	57
	58	#if defined(CONFIG_PCI)
96e48cf6 WD	59	#define CONFIG_PCI_PNP 1
96e48cf6 WD	60	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	61	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
96e48cf6 WD	62
	63	#define CONFIG_PCI_MEM_BUS 0x40000000
	64	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	65	#define CONFIG_PCI_MEM_SIZE 0x10000000
	66
	67	#define CONFIG_PCI_IO_BUS 0x50000000
	68	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	69	#define CONFIG_PCI_IO_SIZE 0x01000000
b66a9383	70	#endif
96e48cf6	71
6d0f6bcf	72	#define CONFIG_SYS_XLB_PIPELINING 1
e1599e83	73
96e48cf6	74	#define CONFIG_NET_MULTI 1
63ff004c	75	#define CONFIG_MII 1
96e48cf6	76	#define CONFIG_EEPRO100 1
6d0f6bcf	77	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
f54ebdfa	78	#define CONFIG_NS8382X 1
96e48cf6	79
132ba5fd WD	80	/* Partitions */
	81	#define CONFIG_MAC_PARTITION
	82	#define CONFIG_DOS_PARTITION
64f70bed	83	#define CONFIG_ISO_PARTITION
132ba5fd	84
80885a9d	85	/* USB */
ae3b770e	86	#define CONFIG_USB_OHCI_NEW
80885a9d	87	#define CONFIG_USB_STORAGE
6d0f6bcf JCPV	88	#define CONFIG_SYS_OHCI_BE_CONTROLLER
	89	#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
	90	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	91	#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
	92	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
	93	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
ae3b770e	94
414eec35 WD	95	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
414eec35 WD	96
348f258f	97
945af8d7	98	/*
11799434	99	* BOOTP options
945af8d7	100	*/
11799434 JL	101	#define CONFIG_BOOTP_BOOTFILESIZE
	102	#define CONFIG_BOOTP_BOOTPATH
	103	#define CONFIG_BOOTP_GATEWAY
	104	#define CONFIG_BOOTP_HOSTNAME
	105
	106
945af8d7	107	/*
348f258f	108	* Command line configuration.
945af8d7	109	*/
348f258f JL	110	#include <config_cmd_default.h>
	111
	112	#define CONFIG_CMD_EEPROM
	113	#define CONFIG_CMD_FAT
	114	#define CONFIG_CMD_I2C
	115	#define CONFIG_CMD_IDE
	116	#define CONFIG_CMD_NFS
	117	#define CONFIG_CMD_SNTP
11799434 JL	118	#define CONFIG_CMD_USB
	119
	120	#if defined(CONFIG_PCI)
	121	#define CONFIG_CMD_PCI
	122	#endif
348f258f	123
945af8d7	124
5cf9da48	125	#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
6d0f6bcf JCPV	126	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	127	# define CONFIG_SYS_LOWBOOT16 1
5cf9da48 WD	128	#endif
5cf9da48 WD	129	#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
09e4b0c5	130	#if defined(CONFIG_LITE5200B)
6d0f6bcf	131	# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
09e4b0c5	132	#else
6d0f6bcf JCPV	133	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	134	# define CONFIG_SYS_LOWBOOT08 1
5cf9da48	135	#endif
09e4b0c5	136	#endif
5cf9da48	137
945af8d7 WD	138	/*
	139	* Autobooting
	140	*/
	141	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
5cf9da48 WD	142
5cf9da48 WD	143	#define CONFIG_PREBOOT "echo;" \
32bf3d14	144	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
5cf9da48 WD	145	"echo"
	146
	147	#undef CONFIG_BOOTARGS
	148
	149	#define CONFIG_EXTRA_ENV_SETTINGS \
	150	"netdev=eth0\0" \
	151	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	152	"nfsroot=${serverip}:${rootpath}\0" \
5cf9da48	153	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	154	"addip=setenv bootargs ${bootargs} " \
	155	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	156	":${hostname}:${netdev}:off panic=1\0" \
5cf9da48	157	"flash_nfs=run nfsargs addip;" \
fe126d8b	158	"bootm ${kernel_addr}\0" \
5cf9da48	159	"flash_self=run ramargs addip;" \
fe126d8b WD	160	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	161	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
5cf9da48 WD	162	"rootpath=/opt/eldk/ppc_82xx\0" \
	163	"bootfile=/tftpboot/MPC5200/uImage\0" \
	164	""
	165
	166	#define CONFIG_BOOTCOMMAND "run flash_self"
945af8d7	167
acf98e7f WD	168	/*
	169	* IPB Bus clocking configuration.
	170	*/
09e4b0c5	171	#if defined(CONFIG_LITE5200B)
6d0f6bcf	172	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
09e4b0c5	173	#else
6d0f6bcf	174	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
acf98e7f	175	#endif
e59581c5 SR	176
e59581c5 SR	177	/* pass open firmware flat tree */
cf2817a8	178	#define CONFIG_OF_LIBFDT 1
e59581c5 SR	179	#define CONFIG_OF_BOARD_SETUP 1
e59581c5 SR	180
e59581c5 SR	181	#define OF_CPU "PowerPC,5200@0"
e59581c5 SR	182	#define OF_SOC "soc5200@f0000000"
39f23cd9	183	#define OF_TBCLK (bd->bi_busfreq / 4)
e59581c5 SR	184	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
e59581c5 SR	185
945af8d7 WD	186	/*
	187	* I2C configuration
	188	*/
531716e1	189	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	190	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
ab209d51	191
6d0f6bcf JCPV	192	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	193	#define CONFIG_SYS_I2C_SLAVE 0x7F
531716e1 WD	194
	195	/*
	196	* EEPROM configuration
	197	*/
6d0f6bcf JCPV	198	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	199	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	200	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	201	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
945af8d7 WD	202
	203	/*
	204	* Flash configuration
	205	*/
09e4b0c5	206	#if defined(CONFIG_LITE5200B)
6d0f6bcf JCPV	207	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	208	#define CONFIG_SYS_FLASH_SIZE 0x01000000
	209	#if !defined(CONFIG_SYS_LOWBOOT)
	210	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
	211	#else /* CONFIG_SYS_LOWBOOT */
	212	#if defined(CONFIG_SYS_LOWBOOT08)
	213	# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
09e4b0c5	214	#endif
6d0f6bcf JCPV	215	#if defined(CONFIG_SYS_LOWBOOT16)
6d0f6bcf JCPV	216	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
09e4b0c5	217	#endif
6d0f6bcf	218	#endif /* CONFIG_SYS_LOWBOOT */
09e4b0c5	219	#else /* !CONFIG_LITE5200B (IceCube)*/
6d0f6bcf JCPV	220	#define CONFIG_SYS_FLASH_BASE 0xFF000000
	221	#define CONFIG_SYS_FLASH_SIZE 0x01000000
	222	#if !defined(CONFIG_SYS_LOWBOOT)
	223	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
	224	#else /* CONFIG_SYS_LOWBOOT */
	225	#if defined(CONFIG_SYS_LOWBOOT08)
	226	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
5cf9da48	227	#endif
6d0f6bcf JCPV	228	#if defined(CONFIG_SYS_LOWBOOT16)
6d0f6bcf JCPV	229	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
7152b1d0	230	#endif
6d0f6bcf	231	#endif /* CONFIG_SYS_LOWBOOT */
09e4b0c5	232	#endif /* CONFIG_LITE5200B */
6d0f6bcf	233	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
7152b1d0	234
6d0f6bcf	235	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
945af8d7	236
6d0f6bcf JCPV	237	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	238	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
945af8d7	239
96e48cf6	240	#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
945af8d7	241
09e4b0c5	242	#if defined(CONFIG_LITE5200B)
00b1883a	243	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	244	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	245	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
09e4b0c5 WD	246	#endif
09e4b0c5 WD	247
945af8d7 WD	248
	249	/*
	250	* Environment settings
	251	*/
5a1aceb0	252	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	253	#define CONFIG_ENV_SIZE 0x10000
09e4b0c5	254	#if defined(CONFIG_LITE5200B)
0e8d1586	255	#define CONFIG_ENV_SECT_SIZE 0x20000
09e4b0c5	256	#else
0e8d1586	257	#define CONFIG_ENV_SECT_SIZE 0x10000
09e4b0c5	258	#endif
96e48cf6	259	#define CONFIG_ENV_OVERWRITE 1
945af8d7 WD	260
	261	/*
	262	* Memory map
	263	*/
6d0f6bcf JCPV	264	#define CONFIG_SYS_MBAR 0xF0000000
	265	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	266	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
945af8d7 WD	267
945af8d7 WD	268	/* Use SRAM until RAM will be available */
6d0f6bcf JCPV	269	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
6d0f6bcf JCPV	270	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
945af8d7 WD	271
945af8d7 WD	272
6d0f6bcf JCPV	273	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	274	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	275	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
945af8d7	276
6d0f6bcf JCPV	277	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	278	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	279	# define CONFIG_SYS_RAMBOOT 1
945af8d7 WD	280	#endif
945af8d7 WD	281
6d0f6bcf JCPV	282	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	283	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	284	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
945af8d7 WD	285
	286	/*
	287	* Ethernet configuration
	288	*/
cbd8a35c	289	#define CONFIG_MPC5xxx_FEC 1
86321fc1	290	#define CONFIG_MPC5xxx_FEC_MII100
04a85b3b	291	/*
86321fc1	292	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
7e780369	293	*/
86321fc1	294	/* #define CONFIG_MPC5xxx_FEC_MII10 */
d4ca31c4	295	#define CONFIG_PHY_ADDR 0x00
945af8d7 WD	296
	297	/*
	298	* GPIO configuration
	299	*/
b2001f27	300	#ifdef CONFIG_MPC5200_DDR
6d0f6bcf	301	#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004
b2001f27	302	#else
6d0f6bcf	303	#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
b2001f27	304	#endif
945af8d7 WD	305
	306	/*
	307	* Miscellaneous configurable options
	308	*/
6d0f6bcf JCPV	309	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	310	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
348f258f	311	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	312	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
945af8d7	313	#else
6d0f6bcf	314	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
945af8d7	315	#endif
6d0f6bcf JCPV	316	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	317	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	318	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
945af8d7	319
6d0f6bcf JCPV	320	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	321	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
945af8d7	322
6d0f6bcf	323	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
945af8d7	324
6d0f6bcf	325	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
945af8d7	326
6d0f6bcf	327	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
348f258f	328	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	329	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
348f258f JL	330	#endif
348f258f JL	331
945af8d7 WD	332	/*
	333	* Various low-level settings
	334	*/
6d0f6bcf JCPV	335	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	336	#define CONFIG_SYS_HID0_FINAL HID0_ICE
945af8d7	337
09e4b0c5	338	#if defined(CONFIG_LITE5200B)
6d0f6bcf JCPV	339	#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
	340	#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
	341	#define CONFIG_SYS_CS1_CFG 0x00047800
	342	#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
	343	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	344	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
	345	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	346	#define CONFIG_SYS_BOOTCS_CFG 0x00047800
09e4b0c5	347	#else /* IceCube aka Lite5200 */
b2001f27 WD	348	#ifdef CONFIG_MPC5200_DDR
b2001f27 WD	349
6d0f6bcf JCPV	350	#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
	351	#define CONFIG_SYS_BOOTCS_SIZE 0x00800000
	352	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	353	#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
	354	#define CONFIG_SYS_CS1_SIZE 0x00800000
	355	#define CONFIG_SYS_CS1_CFG 0x00047800
b2001f27 WD	356
	357	#else /* !CONFIG_MPC5200_DDR */
	358
6d0f6bcf JCPV	359	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	360	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	361	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	362	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	363	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
945af8d7	364
b2001f27	365	#endif /* CONFIG_MPC5200_DDR */
09e4b0c5	366	#endif /CONFIG_LITE5200B /
b2001f27	367
6d0f6bcf JCPV	368	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	369	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
945af8d7	370
6d0f6bcf	371	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
c3f9d493 WD	372
	373	/*-----------------------------------------------------------------------
	374	* USB stuff
	375	*-----------------------------------------------------------------------
	376	*/
4d13cbad WD	377	#define CONFIG_USB_CLOCK 0x0001BBBB
4d13cbad WD	378	#define CONFIG_USB_CONFIG 0x00001000
945af8d7	379
132ba5fd WD	380	/*-----------------------------------------------------------------------
	381	* IDE/ATA stuff Supports IDE harddisk
	382	*-----------------------------------------------------------------------
	383	*/
	384
	385	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	386
	387	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	388	#undef CONFIG_IDE_LED /* LED for ide not supported */
	389
	390	#define CONFIG_IDE_RESET /* reset for ide supported */
	391	#define CONFIG_IDE_PREINIT
	392
6d0f6bcf JCPV	393	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	394	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
132ba5fd	395
6d0f6bcf	396	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
132ba5fd	397
6d0f6bcf	398	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
132ba5fd WD	399
132ba5fd WD	400	/* Offset for data I/O */
6d0f6bcf	401	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
132ba5fd WD	402
132ba5fd WD	403	/* Offset for normal register accesses */
6d0f6bcf	404	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
132ba5fd WD	405
132ba5fd WD	406	/* Offset for alternate registers */
6d0f6bcf	407	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
132ba5fd WD	408
132ba5fd WD	409	/* Interval between registers */
6d0f6bcf	410	#define CONFIG_SYS_ATA_STRIDE 4
132ba5fd	411
64f70bed WD	412	#define CONFIG_ATAPI 1
64f70bed WD	413
945af8d7	414	#endif /* __CONFIG_H */