]>
Commit | Line | Data |
---|---|---|
945af8d7 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2003-2005 |
945af8d7 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | ||
cbd8a35c | 32 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
fd428c05 | 33 | #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ |
945af8d7 WD |
34 | #define CONFIG_ICECUBE 1 /* ... on IceCube board */ |
35 | ||
2ae18241 WD |
36 | /* |
37 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
38 | * 0xFFF00000 boot high (standard configuration) | |
39 | * 0xFF000000 boot low for 16 MiB boards | |
40 | * 0xFF800000 boot low for 8 MiB boards | |
41 | * 0x00100000 boot from RAM (for testing only) | |
42 | */ | |
43 | #ifndef CONFIG_SYS_TEXT_BASE | |
44 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
45 | #endif | |
46 | ||
6d0f6bcf | 47 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
945af8d7 | 48 | |
31d82672 BB |
49 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
50 | ||
945af8d7 WD |
51 | /* |
52 | * Serial console configuration | |
53 | */ | |
54 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
55 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 56 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
945af8d7 | 57 | |
96e48cf6 | 58 | |
96e48cf6 WD |
59 | /* |
60 | * PCI Mapping: | |
61 | * 0x40000000 - 0x4fffffff - PCI Memory | |
62 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
63 | */ | |
b66a9383 RJ |
64 | #define CONFIG_PCI |
65 | ||
66 | #if defined(CONFIG_PCI) | |
96e48cf6 WD |
67 | #define CONFIG_PCI_PNP 1 |
68 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 69 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
96e48cf6 WD |
70 | |
71 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
72 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
73 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
74 | ||
75 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
76 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
77 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
b66a9383 | 78 | #endif |
96e48cf6 | 79 | |
6d0f6bcf | 80 | #define CONFIG_SYS_XLB_PIPELINING 1 |
e1599e83 | 81 | |
96e48cf6 | 82 | #define CONFIG_NET_MULTI 1 |
63ff004c | 83 | #define CONFIG_MII 1 |
96e48cf6 | 84 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 85 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
f54ebdfa | 86 | #define CONFIG_NS8382X 1 |
96e48cf6 | 87 | |
132ba5fd WD |
88 | /* Partitions */ |
89 | #define CONFIG_MAC_PARTITION | |
90 | #define CONFIG_DOS_PARTITION | |
64f70bed | 91 | #define CONFIG_ISO_PARTITION |
132ba5fd | 92 | |
80885a9d | 93 | /* USB */ |
ae3b770e | 94 | #define CONFIG_USB_OHCI_NEW |
80885a9d | 95 | #define CONFIG_USB_STORAGE |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
97 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT | |
98 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
99 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
100 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
101 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
ae3b770e | 102 | |
414eec35 WD |
103 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
104 | ||
348f258f | 105 | |
945af8d7 | 106 | /* |
11799434 | 107 | * BOOTP options |
945af8d7 | 108 | */ |
11799434 JL |
109 | #define CONFIG_BOOTP_BOOTFILESIZE |
110 | #define CONFIG_BOOTP_BOOTPATH | |
111 | #define CONFIG_BOOTP_GATEWAY | |
112 | #define CONFIG_BOOTP_HOSTNAME | |
113 | ||
114 | ||
945af8d7 | 115 | /* |
348f258f | 116 | * Command line configuration. |
945af8d7 | 117 | */ |
348f258f JL |
118 | #include <config_cmd_default.h> |
119 | ||
120 | #define CONFIG_CMD_EEPROM | |
121 | #define CONFIG_CMD_FAT | |
122 | #define CONFIG_CMD_I2C | |
123 | #define CONFIG_CMD_IDE | |
124 | #define CONFIG_CMD_NFS | |
125 | #define CONFIG_CMD_SNTP | |
11799434 JL |
126 | #define CONFIG_CMD_USB |
127 | ||
128 | #if defined(CONFIG_PCI) | |
129 | #define CONFIG_CMD_PCI | |
130 | #endif | |
348f258f | 131 | |
945af8d7 | 132 | |
14d0a02a | 133 | #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ |
6d0f6bcf JCPV |
134 | # define CONFIG_SYS_LOWBOOT 1 |
135 | # define CONFIG_SYS_LOWBOOT16 1 | |
5cf9da48 | 136 | #endif |
14d0a02a | 137 | #if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ |
09e4b0c5 | 138 | #if defined(CONFIG_LITE5200B) |
6d0f6bcf | 139 | # error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B |
09e4b0c5 | 140 | #else |
6d0f6bcf JCPV |
141 | # define CONFIG_SYS_LOWBOOT 1 |
142 | # define CONFIG_SYS_LOWBOOT08 1 | |
5cf9da48 | 143 | #endif |
09e4b0c5 | 144 | #endif |
5cf9da48 | 145 | |
945af8d7 WD |
146 | /* |
147 | * Autobooting | |
148 | */ | |
149 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
5cf9da48 WD |
150 | |
151 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 152 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
5cf9da48 WD |
153 | "echo" |
154 | ||
155 | #undef CONFIG_BOOTARGS | |
156 | ||
157 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
158 | "netdev=eth0\0" \ | |
159 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 160 | "nfsroot=${serverip}:${rootpath}\0" \ |
5cf9da48 | 161 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
162 | "addip=setenv bootargs ${bootargs} " \ |
163 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
164 | ":${hostname}:${netdev}:off panic=1\0" \ | |
5cf9da48 | 165 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 166 | "bootm ${kernel_addr}\0" \ |
5cf9da48 | 167 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
168 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
169 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
5cf9da48 WD |
170 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
171 | "bootfile=/tftpboot/MPC5200/uImage\0" \ | |
172 | "" | |
173 | ||
174 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
945af8d7 | 175 | |
acf98e7f WD |
176 | /* |
177 | * IPB Bus clocking configuration. | |
178 | */ | |
09e4b0c5 | 179 | #if defined(CONFIG_LITE5200B) |
6d0f6bcf | 180 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
09e4b0c5 | 181 | #else |
6d0f6bcf | 182 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
acf98e7f | 183 | #endif |
e59581c5 SR |
184 | |
185 | /* pass open firmware flat tree */ | |
cf2817a8 | 186 | #define CONFIG_OF_LIBFDT 1 |
e59581c5 SR |
187 | #define CONFIG_OF_BOARD_SETUP 1 |
188 | ||
e59581c5 SR |
189 | #define OF_CPU "PowerPC,5200@0" |
190 | #define OF_SOC "soc5200@f0000000" | |
39f23cd9 | 191 | #define OF_TBCLK (bd->bi_busfreq / 4) |
e59581c5 SR |
192 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" |
193 | ||
945af8d7 WD |
194 | /* |
195 | * I2C configuration | |
196 | */ | |
531716e1 | 197 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
6d0f6bcf | 198 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
ab209d51 | 199 | |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
201 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
531716e1 WD |
202 | |
203 | /* | |
204 | * EEPROM configuration | |
205 | */ | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
207 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
208 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
209 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
945af8d7 WD |
210 | |
211 | /* | |
212 | * Flash configuration | |
213 | */ | |
09e4b0c5 | 214 | #if defined(CONFIG_LITE5200B) |
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
216 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
217 | #if !defined(CONFIG_SYS_LOWBOOT) | |
218 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000) | |
219 | #else /* CONFIG_SYS_LOWBOOT */ | |
220 | #if defined(CONFIG_SYS_LOWBOOT08) | |
221 | # error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B | |
09e4b0c5 | 222 | #endif |
6d0f6bcf JCPV |
223 | #if defined(CONFIG_SYS_LOWBOOT16) |
224 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000) | |
09e4b0c5 | 225 | #endif |
6d0f6bcf | 226 | #endif /* CONFIG_SYS_LOWBOOT */ |
09e4b0c5 | 227 | #else /* !CONFIG_LITE5200B (IceCube)*/ |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
229 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
230 | #if !defined(CONFIG_SYS_LOWBOOT) | |
231 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000) | |
232 | #else /* CONFIG_SYS_LOWBOOT */ | |
233 | #if defined(CONFIG_SYS_LOWBOOT08) | |
234 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000) | |
5cf9da48 | 235 | #endif |
6d0f6bcf JCPV |
236 | #if defined(CONFIG_SYS_LOWBOOT16) |
237 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) | |
7152b1d0 | 238 | #endif |
6d0f6bcf | 239 | #endif /* CONFIG_SYS_LOWBOOT */ |
09e4b0c5 | 240 | #endif /* CONFIG_LITE5200B */ |
6d0f6bcf | 241 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ |
7152b1d0 | 242 | |
6d0f6bcf | 243 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
945af8d7 | 244 | |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
246 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
945af8d7 | 247 | |
96e48cf6 | 248 | #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ |
945af8d7 | 249 | |
09e4b0c5 | 250 | #if defined(CONFIG_LITE5200B) |
00b1883a | 251 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_FLASH_CFI |
253 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START} | |
09e4b0c5 WD |
254 | #endif |
255 | ||
945af8d7 WD |
256 | |
257 | /* | |
258 | * Environment settings | |
259 | */ | |
5a1aceb0 | 260 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 261 | #define CONFIG_ENV_SIZE 0x10000 |
09e4b0c5 | 262 | #if defined(CONFIG_LITE5200B) |
0e8d1586 | 263 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
09e4b0c5 | 264 | #else |
0e8d1586 | 265 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
09e4b0c5 | 266 | #endif |
96e48cf6 | 267 | #define CONFIG_ENV_OVERWRITE 1 |
945af8d7 WD |
268 | |
269 | /* | |
270 | * Memory map | |
271 | */ | |
6d0f6bcf JCPV |
272 | #define CONFIG_SYS_MBAR 0xF0000000 |
273 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
274 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
945af8d7 WD |
275 | |
276 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 277 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 278 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
945af8d7 WD |
279 | |
280 | ||
25ddd1fb | 281 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 282 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
945af8d7 | 283 | |
14d0a02a | 284 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
285 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
286 | # define CONFIG_SYS_RAMBOOT 1 | |
945af8d7 WD |
287 | #endif |
288 | ||
6d0f6bcf | 289 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
d2e22731 | 290 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ |
6d0f6bcf | 291 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
945af8d7 WD |
292 | |
293 | /* | |
294 | * Ethernet configuration | |
295 | */ | |
cbd8a35c | 296 | #define CONFIG_MPC5xxx_FEC 1 |
86321fc1 | 297 | #define CONFIG_MPC5xxx_FEC_MII100 |
04a85b3b | 298 | /* |
86321fc1 | 299 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
7e780369 | 300 | */ |
86321fc1 | 301 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
d4ca31c4 | 302 | #define CONFIG_PHY_ADDR 0x00 |
945af8d7 WD |
303 | |
304 | /* | |
305 | * GPIO configuration | |
306 | */ | |
b2001f27 | 307 | #ifdef CONFIG_MPC5200_DDR |
6d0f6bcf | 308 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004 |
b2001f27 | 309 | #else |
6d0f6bcf | 310 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 |
b2001f27 | 311 | #endif |
945af8d7 WD |
312 | |
313 | /* | |
314 | * Miscellaneous configurable options | |
315 | */ | |
6d0f6bcf JCPV |
316 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
317 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
348f258f | 318 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 319 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
945af8d7 | 320 | #else |
6d0f6bcf | 321 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
945af8d7 | 322 | #endif |
6d0f6bcf JCPV |
323 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
324 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
325 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
945af8d7 | 326 | |
d2e22731 WD |
327 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
328 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ | |
329 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
330 | ||
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
332 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
945af8d7 | 333 | |
6d0f6bcf | 334 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
945af8d7 | 335 | |
6d0f6bcf | 336 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
945af8d7 | 337 | |
6d0f6bcf | 338 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
348f258f | 339 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 340 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
348f258f JL |
341 | #endif |
342 | ||
945af8d7 WD |
343 | /* |
344 | * Various low-level settings | |
345 | */ | |
6d0f6bcf JCPV |
346 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
347 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
945af8d7 | 348 | |
09e4b0c5 | 349 | #if defined(CONFIG_LITE5200B) |
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE |
351 | #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE | |
352 | #define CONFIG_SYS_CS1_CFG 0x00047800 | |
353 | #define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE) | |
354 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
355 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START | |
356 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
357 | #define CONFIG_SYS_BOOTCS_CFG 0x00047800 | |
09e4b0c5 | 358 | #else /* IceCube aka Lite5200 */ |
b2001f27 WD |
359 | #ifdef CONFIG_MPC5200_DDR |
360 | ||
6d0f6bcf JCPV |
361 | #define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE) |
362 | #define CONFIG_SYS_BOOTCS_SIZE 0x00800000 | |
363 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 | |
364 | #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE | |
365 | #define CONFIG_SYS_CS1_SIZE 0x00800000 | |
366 | #define CONFIG_SYS_CS1_CFG 0x00047800 | |
b2001f27 WD |
367 | |
368 | #else /* !CONFIG_MPC5200_DDR */ | |
369 | ||
6d0f6bcf JCPV |
370 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
371 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
372 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 | |
373 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
374 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
945af8d7 | 375 | |
b2001f27 | 376 | #endif /* CONFIG_MPC5200_DDR */ |
09e4b0c5 | 377 | #endif /*CONFIG_LITE5200B */ |
b2001f27 | 378 | |
6d0f6bcf JCPV |
379 | #define CONFIG_SYS_CS_BURST 0x00000000 |
380 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
945af8d7 | 381 | |
6d0f6bcf | 382 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
c3f9d493 WD |
383 | |
384 | /*----------------------------------------------------------------------- | |
385 | * USB stuff | |
386 | *----------------------------------------------------------------------- | |
387 | */ | |
4d13cbad WD |
388 | #define CONFIG_USB_CLOCK 0x0001BBBB |
389 | #define CONFIG_USB_CONFIG 0x00001000 | |
945af8d7 | 390 | |
132ba5fd WD |
391 | /*----------------------------------------------------------------------- |
392 | * IDE/ATA stuff Supports IDE harddisk | |
393 | *----------------------------------------------------------------------- | |
394 | */ | |
395 | ||
396 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
397 | ||
398 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
399 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
400 | ||
401 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
402 | #define CONFIG_IDE_PREINIT | |
403 | ||
6d0f6bcf JCPV |
404 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
405 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ | |
132ba5fd | 406 | |
6d0f6bcf | 407 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
132ba5fd | 408 | |
6d0f6bcf | 409 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
132ba5fd WD |
410 | |
411 | /* Offset for data I/O */ | |
6d0f6bcf | 412 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
132ba5fd WD |
413 | |
414 | /* Offset for normal register accesses */ | |
6d0f6bcf | 415 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
132ba5fd WD |
416 | |
417 | /* Offset for alternate registers */ | |
6d0f6bcf | 418 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
132ba5fd WD |
419 | |
420 | /* Interval between registers */ | |
6d0f6bcf | 421 | #define CONFIG_SYS_ATA_STRIDE 4 |
132ba5fd | 422 | |
64f70bed WD |
423 | #define CONFIG_ATAPI 1 |
424 | ||
945af8d7 | 425 | #endif /* __CONFIG_H */ |