[people/ms/u-boot.git] / include / configs / IceCube.h

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5XXX		1	/* This is an MPC5xxx CPU */
#define CONFIG_ICECUBE		1	/* ... on IceCube board */

#define CFG_MPC5XXX_CLKIN	33333333 /* ... running at 33MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
#define CONFIG_EEPRO100		1
#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

#define ADD_PCI_CMD 		CFG_CMD_PCI

#else	/* MPC5100 */

#define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */

#endif

/*
 * Supported commands
 */
#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | ADD_PCI_CMD | \
				 CFG_CMD_I2C | CFG_CMD_EEPROM)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
#   define CFG_LOWBOOT	        1
#   define CFG_LOWBOOT16	1
#endif
#if (TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
#   define CFG_LOWBOOT	        1
#   define CFG_LOWBOOT08	1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

#if defined(CONFIG_MPC5200)
/*
 * IPB Bus clocking configuration.
 */
#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
#endif
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN		1
#define CFG_EEPROM_PAGE_WRITE_BITS	3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		0xff000000
#define CFG_FLASH_SIZE		0x01000000
#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x740000 + 0x800000)
#else	/* CFG_LOWBOOT */
#if defined(CFG_LOWBOOT08)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x30000 + 0x800000)
#endif
#if defined(CFG_LOWBOOT16)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x30000)
#endif
#endif	/* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks      */

#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */


/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x10000
#define CFG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CFG_MBAR		0xf0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5XXX_FEC	1
#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */

/*
 * GPIO configuration
 */
#define CFG_GPS_PORT_CONFIG	0x10000004

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x00047801
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0xff000000

#endif /* __CONFIG_H */
Commit	Line	Data
945af8d7 WD	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC5XXX 1 /* This is an MPC5xxx CPU */
	33	#define CONFIG_ICECUBE 1 /* ... on IceCube board */
	34
	35	#define CFG_MPC5XXX_CLKIN 33333333 /* ... running at 33MHz */
	36
	37	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	38	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	39
96e48cf6	40	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
945af8d7 WD	41	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	42	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	43	#endif
	44
	45	/*
	46	* Serial console configuration
	47	*/
	48	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	49	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	50	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	51
96e48cf6 WD	52
	53	#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
	54	/*
	55	* PCI Mapping:
	56	* 0x40000000 - 0x4fffffff - PCI Memory
	57	* 0x50000000 - 0x50ffffff - PCI IO Space
	58	*/
	59	#define CONFIG_PCI 1
	60	#define CONFIG_PCI_PNP 1
	61	#define CONFIG_PCI_SCAN_SHOW 1
	62
	63	#define CONFIG_PCI_MEM_BUS 0x40000000
	64	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	65	#define CONFIG_PCI_MEM_SIZE 0x10000000
	66
	67	#define CONFIG_PCI_IO_BUS 0x50000000
	68	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	69	#define CONFIG_PCI_IO_SIZE 0x01000000
	70
	71	#define CONFIG_NET_MULTI 1
	72	#define CONFIG_EEPRO100 1
	73	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
f54ebdfa	74	#define CONFIG_NS8382X 1
96e48cf6 WD	75
	76	#define ADD_PCI_CMD CFG_CMD_PCI
	77
	78	#else /* MPC5100 */
	79
	80	#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
	81
	82	#endif
	83
945af8d7 WD	84	/*
	85	* Supported commands
	86	*/
531716e1 WD	87	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| ADD_PCI_CMD \| \
531716e1 WD	88	CFG_CMD_I2C \| CFG_CMD_EEPROM)
945af8d7 WD	89
	90	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	91	#include <cmd_confdefs.h>
	92
5cf9da48 WD	93	#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
	94	# define CFG_LOWBOOT 1
	95	# define CFG_LOWBOOT16 1
	96	#endif
	97	#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
	98	# define CFG_LOWBOOT 1
	99	# define CFG_LOWBOOT08 1
	100	#endif
	101
945af8d7 WD	102	/*
	103	* Autobooting
	104	*/
	105	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
5cf9da48 WD	106
	107	#define CONFIG_PREBOOT "echo;" \
	108	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	109	"echo"
	110
	111	#undef CONFIG_BOOTARGS
	112
	113	#define CONFIG_EXTRA_ENV_SETTINGS \
	114	"netdev=eth0\0" \
	115	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	116	"nfsroot=$(serverip):$(rootpath)\0" \
	117	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	118	"addip=setenv bootargs $(bootargs) " \
	119	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	120	":$(hostname):$(netdev):off panic=1\0" \
	121	"flash_nfs=run nfsargs addip;" \
	122	"bootm $(kernel_addr)\0" \
	123	"flash_self=run ramargs addip;" \
	124	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	125	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	126	"rootpath=/opt/eldk/ppc_82xx\0" \
	127	"bootfile=/tftpboot/MPC5200/uImage\0" \
	128	""
	129
	130	#define CONFIG_BOOTCOMMAND "run flash_self"
945af8d7	131
acf98e7f WD	132	#if defined(CONFIG_MPC5200)
	133	/*
	134	* IPB Bus clocking configuration.
	135	*/
	136	#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
	137	#endif
945af8d7 WD	138	/*
	139	* I2C configuration
	140	*/
531716e1	141	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
ab209d51	142	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	143
	144	#define CFG_I2C_SPEED 100000 /* 100 kHz */
531716e1 WD	145	#define CFG_I2C_SLAVE 0x7F
	146
	147	/*
	148	* EEPROM configuration
	149	*/
	150	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	151	#define CFG_I2C_EEPROM_ADDR_LEN 1
	152	#define CFG_EEPROM_PAGE_WRITE_BITS 3
ab209d51	153	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
945af8d7 WD	154
	155	/*
	156	* Flash configuration
	157	*/
7152b1d0 WD	158	#define CFG_FLASH_BASE 0xff000000
7152b1d0 WD	159	#define CFG_FLASH_SIZE 0x01000000
5cf9da48	160	#if !defined(CFG_LOWBOOT)
7152b1d0	161	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000 + 0x800000)
5cf9da48 WD	162	#else /* CFG_LOWBOOT */
	163	#if defined(CFG_LOWBOOT08)
	164	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x30000 + 0x800000)
	165	#endif
	166	#if defined(CFG_LOWBOOT16)
	167	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x30000)
7152b1d0	168	#endif
5cf9da48 WD	169	#endif /* CFG_LOWBOOT */
5cf9da48 WD	170	#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
7152b1d0	171
945af8d7 WD	172	#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	173
	174	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	175	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	176
96e48cf6	177	#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
945af8d7 WD	178
	179
	180	/*
	181	* Environment settings
	182	*/
96e48cf6	183	#define CFG_ENV_IS_IN_FLASH 1
945af8d7	184	#define CFG_ENV_SIZE 0x10000
96e48cf6 WD	185	#define CFG_ENV_SECT_SIZE 0x10000
96e48cf6 WD	186	#define CONFIG_ENV_OVERWRITE 1
945af8d7 WD	187
	188	/*
	189	* Memory map
	190	*/
	191	#define CFG_MBAR 0xf0000000
	192	#define CFG_SDRAM_BASE 0x00000000
e0ac62d7	193	#define CFG_DEFAULT_MBAR 0x80000000
945af8d7 WD	194
	195	/* Use SRAM until RAM will be available */
	196	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	197	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	198
	199
	200	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	201	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	202	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	203
	204	#define CFG_MONITOR_BASE TEXT_BASE
	205	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
96e48cf6	206	# define CFG_RAMBOOT 1
945af8d7 WD	207	#endif
	208
	209	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	210	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	211	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	212
	213	/*
	214	* Ethernet configuration
	215	*/
945af8d7	216	#define CONFIG_MPC5XXX_FEC 1
35656de7	217	#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
945af8d7 WD	218
	219	/*
	220	* GPIO configuration
	221	*/
c3d98ed9	222	#define CFG_GPS_PORT_CONFIG 0x10000004
945af8d7 WD	223
	224	/*
	225	* Miscellaneous configurable options
	226	*/
	227	#define CFG_LONGHELP /* undef to save memory */
	228	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	229	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	230	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	231	#else
	232	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	233	#endif
	234	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	235	#define CFG_MAXARGS 16 /* max number of command args */
	236	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	237
	238	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	239	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	240
	241	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	242
	243	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	244
	245	/*
	246	* Various low-level settings
	247	*/
b13fb01a	248	#if defined(CONFIG_MPC5200)
4f7cb08e WD	249	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
4f7cb08e WD	250	#define CFG_HID0_FINAL HID0_ICE
b13fb01a WD	251	#else
	252	#define CFG_HID0_INIT 0
	253	#define CFG_HID0_FINAL 0
	254	#endif
945af8d7 WD	255
	256	#define CFG_BOOTCS_START CFG_FLASH_BASE
	257	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	258	#define CFG_BOOTCS_CFG 0x00047801
	259	#define CFG_CS0_START CFG_FLASH_BASE
	260	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	261
	262	#define CFG_CS_BURST 0x00000000
	263	#define CFG_CS_DEADCYCLE 0x33333333
	264
	265	#define CFG_RESET_ADDRESS 0xff000000
	266
	267	#endif /* __CONFIG_H */