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db01a2ea WD |
1 | /* |
2 | * (C) Copyright 2003 Picture Elements, Inc. | |
3 | * Stephen Williams <steve@icarus.com> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options for the JSE board | |
33 | * (Theoretically easy to change, but the board is fixed.) | |
34 | */ | |
35 | ||
36 | #define CONFIG_JSE 1 | |
37 | /* JSE has a PPC405GPr */ | |
38 | #define CONFIG_405GP 1 | |
39 | /* ... which is a 4xxx series */ | |
40 | #define CONFIG_4xx 1 | |
41 | /* ... with a 33MHz OSC. connected to the SysCLK input */ | |
42 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
43 | /* ... with on-chip memory here (4KBytes) */ | |
6d0f6bcf JCPV |
44 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000 |
45 | #define CONFIG_SYS_OCM_DATA_SIZE 0x00001000 | |
db01a2ea | 46 | /* Do not set up locked dcache as init ram. */ |
6d0f6bcf | 47 | #undef CONFIG_SYS_INIT_DCACHE_CS |
db01a2ea WD |
48 | |
49 | /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ | |
50 | #define CONFIG_SYSTEMACE 1 | |
6d0f6bcf JCPV |
51 | #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000 |
52 | #define CONFIG_SYS_SYSTEMACE_WIDTH 8 | |
db01a2ea WD |
53 | #define CONFIG_DOS_PARTITION 1 |
54 | ||
55 | /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ | |
6d0f6bcf | 56 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
db01a2ea | 57 | /* ... place INIT RAM in the OCM address */ |
6d0f6bcf | 58 | # define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR |
db01a2ea | 59 | /* ... give it the whole init ram */ |
6d0f6bcf | 60 | # define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE |
db01a2ea | 61 | /* ... Shave a bit off the end for global data */ |
6d0f6bcf JCPV |
62 | # define CONFIG_SYS_GBL_DATA_SIZE 128 |
63 | # define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
db01a2ea | 64 | /* ... and place the stack pointer at the top of what's left. */ |
6d0f6bcf | 65 | # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
db01a2ea WD |
66 | |
67 | /* Enable board_pre_init function */ | |
68 | #define CONFIG_BOARD_PRE_INIT 1 | |
69 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
70 | /* Disable post-clk setup init function */ | |
71 | #undef CONFIG_BOARD_POSTCLK_INIT | |
72 | /* Disable call to post_init_f: late init function. */ | |
73 | #undef CONFIG_POST | |
74 | /* Enable DRAM test. */ | |
6d0f6bcf | 75 | #define CONFIG_SYS_DRAM_TEST 1 |
db01a2ea WD |
76 | /* Enable misc_init_r function. */ |
77 | #define CONFIG_MISC_INIT_R 1 | |
78 | ||
79 | /* JSE has EEPROM chips that are good for environment. */ | |
9314cee6 | 80 | #undef CONFIG_ENV_IS_IN_NVRAM |
5a1aceb0 | 81 | #undef CONFIG_ENV_IS_IN_FLASH |
bb1f8b4f | 82 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
93f6d725 | 83 | #undef CONFIG_ENV_IS_NOWHERE |
db01a2ea WD |
84 | |
85 | /* This is the 7bit address of the device, not including P. */ | |
6d0f6bcf | 86 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
db01a2ea | 87 | /* After the device address, need one more address byte. */ |
6d0f6bcf | 88 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
db01a2ea | 89 | /* The EEPROM is 512 bytes. */ |
6d0f6bcf | 90 | #define CONFIG_SYS_EEPROM_SIZE 512 |
db01a2ea | 91 | /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 |
93 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
db01a2ea | 94 | /* Put the environment in the second half. */ |
0e8d1586 JCPV |
95 | #define CONFIG_ENV_OFFSET 0x00 |
96 | #define CONFIG_ENV_SIZE 512 | |
db01a2ea WD |
97 | |
98 | ||
99 | /* The JSE connects UART1 to the console tap connector. */ | |
100 | #define CONFIG_UART1_CONSOLE 1 | |
101 | /* Set console baudrate to 9600 */ | |
102 | #define CONFIG_BAUDRATE 9600 | |
103 | ||
104 | /* Size (bytes) of interrupt driven serial port buffer. | |
105 | * Set to 0 to use polling instead of interrupts. | |
106 | * Setting to 0 will also disable RTS/CTS handshaking. | |
107 | */ | |
108 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
109 | ||
110 | /* | |
111 | * Configuration related to auto-boot. | |
112 | * | |
113 | * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait | |
114 | * before resorting to autoboot. This value can be overridden by the | |
115 | * bootdelay environment variable. | |
116 | * | |
117 | * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the | |
118 | * user that an autoboot will happen. | |
119 | * | |
120 | * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will | |
121 | * execute to boot the JSE. This loads the uimage and initrd.img files | |
122 | * from CompactFlash into memory, then boots them from memory. | |
123 | * | |
124 | * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get | |
125 | * it going on the JSE. | |
126 | */ | |
127 | #define CONFIG_BOOTDELAY 5 | |
128 | #define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw" | |
129 | #define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000" | |
130 | ||
131 | ||
132 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 133 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
db01a2ea | 134 | |
96e21f86 | 135 | #define CONFIG_PPC4xx_EMAC |
db01a2ea WD |
136 | #define CONFIG_MII 1 /* MII PHY management */ |
137 | #define CONFIG_PHY_ADDR 1 /* PHY address */ | |
18cc7afd | 138 | #define CONFIG_NET_MULTI |
db01a2ea | 139 | |
348f258f | 140 | |
659e2f67 JL |
141 | /* |
142 | * BOOTP options | |
143 | */ | |
144 | #define CONFIG_BOOTP_BOOTFILESIZE | |
145 | #define CONFIG_BOOTP_BOOTPATH | |
146 | #define CONFIG_BOOTP_GATEWAY | |
147 | #define CONFIG_BOOTP_HOSTNAME | |
148 | ||
149 | ||
348f258f JL |
150 | /* |
151 | * Command line configuration. | |
152 | */ | |
153 | #include <config_cmd_default.h> | |
154 | ||
155 | #define CONFIG_CMD_DHCP | |
156 | #define CONFIG_CMD_EEPROM | |
157 | #define CONFIG_CMD_ELF | |
158 | #define CONFIG_CMD_FAT | |
159 | #define CONFIG_CMD_FLASH | |
160 | #define CONFIG_CMD_IRQ | |
161 | #define CONFIG_CMD_MII | |
162 | #define CONFIG_CMD_NET | |
163 | #define CONFIG_CMD_PCI | |
164 | #define CONFIG_CMD_PING | |
165 | ||
db01a2ea WD |
166 | |
167 | /* watchdog disabled */ | |
168 | #undef CONFIG_WATCHDOG | |
169 | /* SPD EEPROM (sdram speed config) disabled */ | |
2471111d | 170 | #undef CONFIG_SPD_EEPROM |
db01a2ea WD |
171 | #undef SPD_EEPROM_ADDRESS |
172 | ||
173 | /* | |
174 | * Miscellaneous configurable options | |
175 | */ | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
177 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
db01a2ea | 178 | |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
180 | #ifdef CONFIG_SYS_HUSH_PARSER | |
181 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
db01a2ea WD |
182 | #endif |
183 | ||
348f258f | 184 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 185 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
db01a2ea | 186 | #else |
6d0f6bcf | 187 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
db01a2ea | 188 | #endif |
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
190 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
191 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
db01a2ea | 192 | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
194 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
db01a2ea WD |
195 | |
196 | /* | |
6d0f6bcf JCPV |
197 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
198 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
199 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. | |
db01a2ea WD |
200 | * The Linux BASE_BAUD define should match this configuration. |
201 | * baseBaud = cpuClock/(uartDivisor*16) | |
6d0f6bcf | 202 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
db01a2ea WD |
203 | * set Linux BASE_BAUD to 403200. |
204 | */ | |
6d0f6bcf JCPV |
205 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
206 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
207 | #define CONFIG_SYS_BASE_BAUD 691200 | |
db01a2ea WD |
208 | |
209 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 210 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
db01a2ea WD |
211 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
212 | ||
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
214 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
db01a2ea | 215 | |
6d0f6bcf | 216 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
db01a2ea WD |
217 | |
218 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
219 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
d0b0dcaa | 220 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
222 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
db01a2ea WD |
223 | |
224 | ||
225 | /*----------------------------------------------------------------------- | |
226 | * PCI stuff | |
227 | *----------------------------------------------------------------------- | |
228 | */ | |
229 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ | |
230 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
231 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
232 | ||
233 | #define CONFIG_PCI /* include pci support */ | |
234 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
235 | #undef CONFIG_PCI_PNP /* do pci plug-and-play */ | |
236 | /* resource configuration */ | |
237 | ||
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
239 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ | |
240 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
241 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
242 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
243 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
244 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
245 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
db01a2ea WD |
246 | |
247 | /*----------------------------------------------------------------------- | |
248 | * External peripheral base address | |
249 | *----------------------------------------------------------------------- | |
250 | */ | |
251 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
252 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
253 | ||
6d0f6bcf JCPV |
254 | #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 |
255 | #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 | |
256 | #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 | |
db01a2ea WD |
257 | |
258 | /*----------------------------------------------------------------------- | |
259 | * Start addresses for the final memory configuration | |
260 | * (Set up by the startup code) | |
6d0f6bcf | 261 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
db01a2ea | 262 | */ |
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
264 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 | |
265 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
266 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
267 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
db01a2ea WD |
268 | |
269 | /* | |
270 | * For booting Linux, the board info and command line data | |
271 | * have to be in the first 8 MB of memory, since this is | |
272 | * the maximum mapped by the Linux kernel during initialization. | |
273 | */ | |
6d0f6bcf | 274 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
db01a2ea WD |
275 | |
276 | /*----------------------------------------------------------------------- | |
277 | * FLASH organization | |
278 | */ | |
6d0f6bcf JCPV |
279 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
280 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
db01a2ea | 281 | |
6d0f6bcf JCPV |
282 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
283 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
db01a2ea | 284 | |
db01a2ea WD |
285 | /* |
286 | * Init Memory Controller: | |
287 | * | |
288 | * BR0/1 and OR0/1 (FLASH) | |
289 | */ | |
290 | ||
6d0f6bcf | 291 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
db01a2ea WD |
292 | #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
293 | ||
294 | ||
295 | /* Configuration Port location */ | |
296 | #define CONFIG_PORT_ADDR 0xF0000500 | |
297 | ||
298 | ||
299 | /* | |
300 | * Internal Definitions | |
301 | * | |
302 | * Boot Flags | |
303 | */ | |
304 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
305 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
306 | ||
348f258f | 307 | #if defined(CONFIG_CMD_KGDB) |
db01a2ea WD |
308 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
309 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
310 | #endif | |
311 | #endif /* __CONFIG_H */ |