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b79316f2 SR |
1 | /* |
2 | * (C) Copyright 2004 Sandburst Corporation | |
3 | * | |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
b79316f2 SR |
5 | */ |
6 | ||
7 | /************************************************************************ | |
8 | * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference | |
3d078ce6 | 9 | * design. |
b79316f2 SR |
10 | ***********************************************************************/ |
11 | ||
12 | /* | |
13 | * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $ | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
20 | /*----------------------------------------------------------------------- | |
21 | * High Level Configuration Options | |
22 | *----------------------------------------------------------------------*/ | |
3d078ce6 WD |
23 | #define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ |
24 | #define CONFIG_440GX 1 /* Specifc GX support */ | |
efa35cf1 | 25 | #define CONFIG_440 1 /* ... PPC440 family */ |
3d078ce6 | 26 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
b79316f2 | 27 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
3d078ce6 WD |
28 | #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ |
29 | #define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ | |
2ae18241 WD |
30 | |
31 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 | |
32 | ||
6d0f6bcf | 33 | #undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/ |
3d078ce6 | 34 | #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ |
b79316f2 SR |
35 | |
36 | #define CONFIG_VERY_BIG_RAM 1 | |
37 | #define CONFIG_VERSION_VARIABLE | |
38 | ||
39 | #define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design" | |
40 | ||
41 | /*----------------------------------------------------------------------- | |
42 | * Base addresses -- Note these are effective addresses where the | |
43 | * actual resources get mapped (not physical addresses) | |
44 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
45 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
46 | #define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ | |
47 | #define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ | |
48 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
6d0f6bcf JCPV |
49 | #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
50 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
51 | ||
52 | #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) | |
53 | #define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000) | |
54 | #define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000) | |
55 | #define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000) | |
56 | #define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) | |
b79316f2 SR |
57 | |
58 | /* Here for completeness */ | |
6d0f6bcf | 59 | #define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000) |
b79316f2 SR |
60 | |
61 | /*----------------------------------------------------------------------- | |
62 | * Initial RAM & stack pointer (placed in internal SRAM) | |
63 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
64 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
65 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE | |
66 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ | |
553f0982 | 67 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
b79316f2 | 68 | |
25ddd1fb | 69 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
800eb096 | 70 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
b79316f2 | 71 | |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ |
73 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ | |
b79316f2 SR |
74 | |
75 | /*----------------------------------------------------------------------- | |
76 | * Serial Port | |
77 | *----------------------------------------------------------------------*/ | |
550650dd SR |
78 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
79 | #define CONFIG_SYS_NS16550 | |
80 | #define CONFIG_SYS_NS16550_SERIAL | |
81 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
82 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
b79316f2 SR |
83 | #define CONFIG_BAUDRATE 9600 |
84 | ||
6d0f6bcf | 85 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
b79316f2 SR |
86 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
87 | ||
88 | /*----------------------------------------------------------------------- | |
89 | * NVRAM/RTC | |
90 | * | |
91 | * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. | |
92 | * The DS1743 code assumes this condition (i.e. -- it assumes the base | |
93 | * address for the RTC registers is: | |
94 | * | |
6d0f6bcf | 95 | * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE |
b79316f2 SR |
96 | * |
97 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 98 | #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ |
3d078ce6 | 99 | #define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ |
b79316f2 SR |
100 | |
101 | /*----------------------------------------------------------------------- | |
102 | * FLASH related | |
103 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
105 | #define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */ | |
b79316f2 | 106 | |
6d0f6bcf JCPV |
107 | #undef CONFIG_SYS_FLASH_CHECKSUM |
108 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ | |
109 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ | |
b79316f2 SR |
110 | |
111 | /*----------------------------------------------------------------------- | |
112 | * DDR SDRAM | |
113 | *----------------------------------------------------------------------*/ | |
3d078ce6 WD |
114 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ |
115 | #define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ | |
b79316f2 SR |
116 | |
117 | /*----------------------------------------------------------------------- | |
118 | * I2C | |
119 | *----------------------------------------------------------------------*/ | |
880540de DE |
120 | #define CONFIG_SYS_I2C |
121 | #define CONFIG_SYS_I2C_PPC4XX | |
122 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
123 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
124 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
125 | #define CONFIG_SYS_I2C_PPC4XX_CH1 | |
126 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */ | |
127 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F | |
128 | #define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */ | |
b79316f2 SR |
129 | |
130 | /*----------------------------------------------------------------------- | |
131 | * Environment | |
132 | *----------------------------------------------------------------------*/ | |
9314cee6 | 133 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ |
5a1aceb0 | 134 | #undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */ |
bb1f8b4f | 135 | #undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ |
3d078ce6 | 136 | #define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ |
b79316f2 | 137 | |
0e8d1586 | 138 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */ |
6d0f6bcf | 139 | #define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR) |
b79316f2 | 140 | |
3d078ce6 | 141 | #define CONFIG_BOOTDELAY 5 /* 5 second autoboot */ |
b79316f2 | 142 | |
3d078ce6 | 143 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ |
6d0f6bcf | 144 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
b79316f2 SR |
145 | |
146 | /*----------------------------------------------------------------------- | |
147 | * Networking | |
148 | *----------------------------------------------------------------------*/ | |
96e21f86 | 149 | #define CONFIG_PPC4xx_EMAC |
3d078ce6 | 150 | #define CONFIG_MII 1 /* MII PHY management */ |
3d078ce6 WD |
151 | #define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ |
152 | #define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ | |
153 | #define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ | |
154 | #define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ | |
b79316f2 SR |
155 | #define CONFIG_HAS_ETH0 |
156 | #define CONFIG_HAS_ETH1 | |
157 | #define CONFIG_HAS_ETH2 | |
158 | #define CONFIG_HAS_ETH3 | |
d6c61aab | 159 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
3d078ce6 WD |
160 | #define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ |
161 | #define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ | |
162 | #define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ | |
b79316f2 | 163 | #define CONFIG_PHY_RESET_DELAY 1000 |
3d078ce6 WD |
164 | #define CONFIG_NETMASK 255.255.0.0 |
165 | #define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ | |
166 | #define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ | |
6d0f6bcf | 167 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ |
b79316f2 SR |
168 | |
169 | ||
659e2f67 JL |
170 | /* |
171 | * BOOTP options | |
172 | */ | |
173 | #define CONFIG_BOOTP_BOOTFILESIZE | |
174 | #define CONFIG_BOOTP_BOOTPATH | |
175 | #define CONFIG_BOOTP_GATEWAY | |
176 | #define CONFIG_BOOTP_HOSTNAME | |
177 | ||
178 | ||
348f258f JL |
179 | /* |
180 | * Command line configuration. | |
181 | */ | |
182 | #include <config_cmd_default.h> | |
183 | ||
184 | #define CONFIG_CMD_PCI | |
185 | #define CONFIG_CMD_IRQ | |
186 | #define CONFIG_CMD_I2C | |
187 | #define CONFIG_CMD_DHCP | |
188 | #define CONFIG_CMD_DATE | |
189 | #define CONFIG_CMD_BEDBUG | |
190 | #define CONFIG_CMD_PING | |
191 | #define CONFIG_CMD_DIAG | |
192 | #define CONFIG_CMD_MII | |
193 | #define CONFIG_CMD_NET | |
194 | #define CONFIG_CMD_ELF | |
195 | #define CONFIG_CMD_IDE | |
196 | #define CONFIG_CMD_FAT | |
197 | ||
b79316f2 SR |
198 | |
199 | /* Include NetConsole support */ | |
200 | #define CONFIG_NETCONSOLE | |
201 | ||
202 | /* Include auto complete with tabs */ | |
203 | #define CONFIG_AUTO_COMPLETE 1 | |
6d0f6bcf | 204 | #define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ |
b79316f2 | 205 | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
207 | #define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */ | |
b79316f2 | 208 | |
6d0f6bcf | 209 | #define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */ |
b79316f2 SR |
210 | |
211 | ||
212 | /*----------------------------------------------------------------------- | |
213 | * Console Buffer | |
214 | *----------------------------------------------------------------------*/ | |
348f258f | 215 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 216 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
b79316f2 | 217 | #else |
6d0f6bcf | 218 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b79316f2 | 219 | #endif |
6d0f6bcf | 220 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
3d078ce6 | 221 | /* Print Buffer Size */ |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ |
223 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ | |
b79316f2 SR |
224 | |
225 | /*----------------------------------------------------------------------- | |
226 | * Memory Test | |
227 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
229 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
b79316f2 SR |
230 | |
231 | /*----------------------------------------------------------------------- | |
232 | * Compact Flash (in true IDE mode) | |
233 | *----------------------------------------------------------------------*/ | |
234 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
235 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
236 | ||
3d078ce6 | 237 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
239 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ | |
b79316f2 | 240 | |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000 |
242 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
243 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ | |
244 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ | |
245 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ | |
b79316f2 | 246 | |
6d0f6bcf | 247 | #define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride |
3d078ce6 WD |
248 | to get to the correct offset */ |
249 | #define CONFIG_DOS_PARTITION 1 /* Include dos partition */ | |
b79316f2 SR |
250 | |
251 | /*----------------------------------------------------------------------- | |
252 | * PCI | |
253 | *----------------------------------------------------------------------*/ | |
254 | /* General PCI */ | |
3d078ce6 | 255 | #define CONFIG_PCI /* include pci support */ |
842033e6 | 256 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
3d078ce6 WD |
257 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
258 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices */ | |
6d0f6bcf | 259 | #define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE) |
b79316f2 SR |
260 | |
261 | /* Board-specific PCI */ | |
6d0f6bcf | 262 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/ |
b79316f2 | 263 | |
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ |
265 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
b79316f2 SR |
266 | |
267 | /* | |
268 | * For booting Linux, the board info and command line data | |
269 | * have to be in the first 8 MB of memory, since this is | |
270 | * the maximum mapped by the Linux kernel during initialization. | |
271 | */ | |
6d0f6bcf | 272 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
b79316f2 | 273 | |
348f258f | 274 | #if defined(CONFIG_CMD_KGDB) |
3d078ce6 | 275 | #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ |
b79316f2 SR |
276 | #endif |
277 | ||
278 | /*----------------------------------------------------------------------- | |
279 | * Miscellaneous configurable options | |
280 | *----------------------------------------------------------------------*/ | |
3d078ce6 | 281 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
6d0f6bcf JCPV |
282 | #define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */ |
283 | #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */ | |
b79316f2 | 284 | |
b79316f2 | 285 | #endif /* __CONFIG_H */ |