[people/ms/u-boot.git] / include / configs / KAREF.h

/*
 * (C) Copyright 2004 Sandburst Corporation
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
 *		    design.
 ***********************************************************************/

/*
 * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
 *
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_KAREF	     1		/* Board is Kamino Ref Variant */
#define CONFIG_440GX		  1	     /* Specifc GX support	*/
#define CONFIG_440		  1	     /* ... PPC440 family	*/
#define CONFIG_4xx		  1	     /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFF80000

#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/

#define CONFIG_VERY_BIG_RAM 1
#define CONFIG_VERSION_VARIABLE

#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/

#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
#define CONFIG_SYS_KAREF_FPGA_BASE   (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
#define CONFIG_SYS_OFEM_FPGA_BASE    (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)

/* Here for completeness */
#define CONFIG_SYS_OFEMAC_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM    1
#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_END      0x2000	     /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE     128	     /* num bytes initial data	*/

#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#define CONFIG_SERIAL_MULTI   1
#define CONFIG_BAUDRATE	      9600

#define CONFIG_SYS_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 * The DS1743 code assumes this condition (i.e. -- it assumes the base
 * address for the RTC registers is:
 *
 *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
 *
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C	      1		     /* I2C hardware support	*/
#undef	CONFIG_SOFT_I2C			     /* I2C !bit-banged		*/
#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
#define CONFIG_SYS_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
#define CONFIG_SYS_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
#define CONFIG_SYS_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
#define CONFIG_I2C_BUS1	      1		     /* Include i2c bus 1 supp	*/


/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
#undef	CONFIG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
#undef	CONFIG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/

#define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)

#define CONFIG_BOOTDELAY      5		    /* 5 second autoboot */

#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/

/*-----------------------------------------------------------------------
 * Networking
 *----------------------------------------------------------------------*/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII	      1		     /* MII PHY management	*/
#define CONFIG_NET_MULTI      1
#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_NETMASK	      255.255.0.0
#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_PING
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT


/* Include NetConsole support */
#define CONFIG_NETCONSOLE

/* Include auto complete with tabs */
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */

#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
#define CONFIG_SYS_PROMPT	      "KaRefDes=> "  /* Monitor Command Prompt	*/

#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
#define CONFIG_SYS_PROMPT_HUSH_PS2    "> "


/*-----------------------------------------------------------------------
 * Console Buffer
 *----------------------------------------------------------------------*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
					     /* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/

/*-----------------------------------------------------------------------
 * Memory Test
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/

/*-----------------------------------------------------------------------
 * Compact Flash (in true IDE mode)
 *----------------------------------------------------------------------*/
#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/

#define CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */

#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
					    to get to the correct offset */
#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/

/*-----------------------------------------------------------------------
 * PCI
 *----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI			     /* include pci support	*/
#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	      0x01	     /* Normal PowerOn: Boot from FLASH */
#define BOOTFLAG_WARM	      0x02	     /* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
#define CONFIG_KGDB_SER_INDEX 2		     /* kgdb serial port	*/
#endif

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */

#define CONFIG_SYS_HZ		      100	     /* decr freq: 1 ms ticks	*/


#endif	/* __CONFIG_H */
Commit	Line	Data
b79316f2 SR	1	/*
	2	* (C) Copyright 2004 Sandburst Corporation
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/************************************************************************
	24	* KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
3d078ce6	25	* design.
b79316f2 SR	26	***********************************************************************/
	27
	28	/*
	29	* $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
	30	*
	31	*/
	32
	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
	35
	36	/*-----------------------------------------------------------------------
	37	* High Level Configuration Options
	38	----------------------------------------------------------------------/
3d078ce6 WD	39	#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
3d078ce6 WD	40	#define CONFIG_440GX 1 /* Specifc GX support */
efa35cf1	41	#define CONFIG_440 1 /* ... PPC440 family */
3d078ce6	42	#define CONFIG_4xx 1 /* ... PPC4xx family */
b79316f2	43	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
3d078ce6 WD	44	#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
3d078ce6 WD	45	#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
2ae18241 WD	46
	47	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
	48
6d0f6bcf	49	#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
3d078ce6	50	#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
b79316f2 SR	51
	52	#define CONFIG_VERY_BIG_RAM 1
	53	#define CONFIG_VERSION_VARIABLE
	54
	55	#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
	56
	57	/*-----------------------------------------------------------------------
	58	* Base addresses -- Note these are effective addresses where the
	59	* actual resources get mapped (not physical addresses)
	60	----------------------------------------------------------------------/
6d0f6bcf JCPV	61	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	62	#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
	63	#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
	64	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
6d0f6bcf JCPV	65	#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
	66	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
	67
	68	#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
	69	#define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
	70	#define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
	71	#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
	72	#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
b79316f2 SR	73
b79316f2 SR	74	/* Here for completeness */
6d0f6bcf	75	#define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
b79316f2 SR	76
	77	/*-----------------------------------------------------------------------
	78	* Initial RAM & stack pointer (placed in internal SRAM)
	79	----------------------------------------------------------------------/
6d0f6bcf JCPV	80	#define CONFIG_SYS_TEMP_STACK_OCM 1
	81	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	82	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
	83	#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
	84	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
b79316f2	85
6d0f6bcf	86	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
800eb096	87	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
b79316f2	88
6d0f6bcf JCPV	89	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
6d0f6bcf JCPV	90	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
b79316f2 SR	91
	92	/*-----------------------------------------------------------------------
	93	* Serial Port
	94	----------------------------------------------------------------------/
550650dd SR	95	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	96	#define CONFIG_SYS_NS16550
	97	#define CONFIG_SYS_NS16550_SERIAL
	98	#define CONFIG_SYS_NS16550_REG_SIZE 1
	99	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
b79316f2 SR	100	#define CONFIG_SERIAL_MULTI 1
	101	#define CONFIG_BAUDRATE 9600
	102
6d0f6bcf	103	#define CONFIG_SYS_BAUDRATE_TABLE \
b79316f2 SR	104	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	105
	106	/*-----------------------------------------------------------------------
	107	* NVRAM/RTC
	108	*
	109	* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
	110	* The DS1743 code assumes this condition (i.e. -- it assumes the base
	111	* address for the RTC registers is:
	112	*
6d0f6bcf	113	* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
b79316f2 SR	114	*
b79316f2 SR	115	----------------------------------------------------------------------/
6d0f6bcf	116	#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
3d078ce6	117	#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
b79316f2 SR	118
	119	/*-----------------------------------------------------------------------
	120	* FLASH related
	121	----------------------------------------------------------------------/
6d0f6bcf JCPV	122	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
6d0f6bcf JCPV	123	#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
b79316f2	124
6d0f6bcf JCPV	125	#undef CONFIG_SYS_FLASH_CHECKSUM
	126	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
	127	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
b79316f2 SR	128
	129	/*-----------------------------------------------------------------------
	130	* DDR SDRAM
	131	----------------------------------------------------------------------/
3d078ce6 WD	132	#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
3d078ce6 WD	133	#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
b79316f2 SR	134
	135	/*-----------------------------------------------------------------------
	136	* I2C
	137	----------------------------------------------------------------------/
3d078ce6 WD	138	#define CONFIG_HARD_I2C 1 /* I2C hardware support */
3d078ce6 WD	139	#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
d0b0dcaa	140	#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
6d0f6bcf JCPV	141	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */
	142	#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
	143	#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
3d078ce6	144	#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
b79316f2 SR	145
	146
	147	/*-----------------------------------------------------------------------
	148	* Environment
	149	----------------------------------------------------------------------/
9314cee6	150	#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
5a1aceb0	151	#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
bb1f8b4f	152	#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
3d078ce6	153	#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
b79316f2	154
0e8d1586	155	#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
6d0f6bcf	156	#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
b79316f2	157
3d078ce6	158	#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
b79316f2	159
3d078ce6	160	#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
6d0f6bcf	161	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
b79316f2 SR	162
	163	/*-----------------------------------------------------------------------
	164	* Networking
	165	----------------------------------------------------------------------/
96e21f86	166	#define CONFIG_PPC4xx_EMAC
3d078ce6	167	#define CONFIG_MII 1 /* MII PHY management */
b79316f2	168	#define CONFIG_NET_MULTI 1
3d078ce6 WD	169	#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
	170	#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
	171	#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
	172	#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
b79316f2 SR	173	#define CONFIG_HAS_ETH0
	174	#define CONFIG_HAS_ETH1
	175	#define CONFIG_HAS_ETH2
	176	#define CONFIG_HAS_ETH3
d6c61aab	177	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
3d078ce6 WD	178	#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
	179	#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
	180	#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
b79316f2	181	#define CONFIG_PHY_RESET_DELAY 1000
3d078ce6 WD	182	#define CONFIG_NETMASK 255.255.0.0
	183	#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
	184	#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
6d0f6bcf	185	#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
b79316f2 SR	186
b79316f2 SR	187
659e2f67 JL	188	/*
	189	* BOOTP options
	190	*/
	191	#define CONFIG_BOOTP_BOOTFILESIZE
	192	#define CONFIG_BOOTP_BOOTPATH
	193	#define CONFIG_BOOTP_GATEWAY
	194	#define CONFIG_BOOTP_HOSTNAME
	195
	196
348f258f JL	197	/*
	198	* Command line configuration.
	199	*/
	200	#include <config_cmd_default.h>
	201
	202	#define CONFIG_CMD_PCI
	203	#define CONFIG_CMD_IRQ
	204	#define CONFIG_CMD_I2C
	205	#define CONFIG_CMD_DHCP
	206	#define CONFIG_CMD_DATE
	207	#define CONFIG_CMD_BEDBUG
	208	#define CONFIG_CMD_PING
	209	#define CONFIG_CMD_DIAG
	210	#define CONFIG_CMD_MII
	211	#define CONFIG_CMD_NET
	212	#define CONFIG_CMD_ELF
	213	#define CONFIG_CMD_IDE
	214	#define CONFIG_CMD_FAT
	215
b79316f2 SR	216
	217	/* Include NetConsole support */
	218	#define CONFIG_NETCONSOLE
	219
	220	/* Include auto complete with tabs */
	221	#define CONFIG_AUTO_COMPLETE 1
6d0f6bcf	222	#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
b79316f2	223
6d0f6bcf JCPV	224	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	225	#define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
b79316f2	226
6d0f6bcf JCPV	227	#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
6d0f6bcf JCPV	228	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
b79316f2 SR	229
	230
	231	/*-----------------------------------------------------------------------
	232	* Console Buffer
	233	----------------------------------------------------------------------/
348f258f	234	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	235	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
b79316f2	236	#else
6d0f6bcf	237	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b79316f2	238	#endif
6d0f6bcf	239	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
3d078ce6	240	/* Print Buffer Size */
6d0f6bcf JCPV	241	#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
6d0f6bcf JCPV	242	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
b79316f2 SR	243
	244	/*-----------------------------------------------------------------------
	245	* Memory Test
	246	----------------------------------------------------------------------/
6d0f6bcf JCPV	247	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	248	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
b79316f2 SR	249
	250	/*-----------------------------------------------------------------------
	251	* Compact Flash (in true IDE mode)
	252	----------------------------------------------------------------------/
	253	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	254	#undef CONFIG_IDE_LED /* no led for ide supported */
	255
3d078ce6	256	#define CONFIG_IDE_RESET /* reset for ide supported */
6d0f6bcf JCPV	257	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
6d0f6bcf JCPV	258	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS1) / max. 1 drives per IDE bus */
b79316f2	259
6d0f6bcf JCPV	260	#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
	261	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	262	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	263	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
	264	#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
b79316f2	265
6d0f6bcf	266	#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
3d078ce6 WD	267	to get to the correct offset */
3d078ce6 WD	268	#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
b79316f2 SR	269
	270	/*-----------------------------------------------------------------------
	271	* PCI
	272	----------------------------------------------------------------------/
	273	/* General PCI */
3d078ce6 WD	274	#define CONFIG_PCI /* include pci support */
	275	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	276	#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
6d0f6bcf	277	#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
b79316f2 SR	278
b79316f2 SR	279	/* Board-specific PCI */
6d0f6bcf	280	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
b79316f2	281
6d0f6bcf JCPV	282	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
6d0f6bcf JCPV	283	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
b79316f2 SR	284
	285	/*
	286	* For booting Linux, the board info and command line data
	287	* have to be in the first 8 MB of memory, since this is
	288	* the maximum mapped by the Linux kernel during initialization.
	289	*/
6d0f6bcf	290	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
b79316f2 SR	291
	292	/*
	293	* Internal Definitions
	294	*
	295	* Boot Flags
	296	*/
3d078ce6 WD	297	#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
3d078ce6 WD	298	#define BOOTFLAG_WARM 0x02 /* Software reboot */
b79316f2	299
348f258f	300	#if defined(CONFIG_CMD_KGDB)
3d078ce6 WD	301	#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
3d078ce6 WD	302	#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
b79316f2 SR	303	#endif
	304
	305	/*-----------------------------------------------------------------------
	306	* Miscellaneous configurable options
	307	----------------------------------------------------------------------/
3d078ce6	308	#undef CONFIG_WATCHDOG /* watchdog disabled */
6d0f6bcf JCPV	309	#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
6d0f6bcf JCPV	310	#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
b79316f2	311
6d0f6bcf	312	#define CONFIG_SYS_HZ 100 /* decr freq: 1 ms ticks */
b79316f2 SR	313
	314
	315	#endif /* __CONFIG_H */