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56f94be3 | 1 | /* |
e604e409 | 2 | * (C) Copyright 2000-2010 |
56f94be3 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
56f94be3 WD |
7 | */ |
8 | ||
9 | /* | |
10 | * board/config.h - configuration options, board specific | |
11 | * Derived from ../tqm8xx/tqm8xx.c | |
12 | */ | |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
21 | ||
22 | #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ | |
23 | #define CONFIG_KUP4K 1 /* ...on a KUP4K module */ | |
24 | ||
2ae18241 WD |
25 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
26 | ||
0608e04d | 27 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
56f94be3 WD |
28 | #undef CONFIG_8xx_CONS_SMC2 |
29 | #undef CONFIG_8xx_CONS_NONE | |
682011ff | 30 | #define CONFIG_BAUDRATE 115200 /* console baudrate */ |
682011ff | 31 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
56f94be3 | 32 | |
56f94be3 WD |
33 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
34 | ||
56f94be3 WD |
35 | #undef CONFIG_BOOTARGS |
36 | ||
0608e04d | 37 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
e604e409 | 38 | "slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \ |
2d941de9 | 39 | "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \ |
e604e409 | 40 | "slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \ |
2d941de9 | 41 | "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \ |
e604e409 HS |
42 | "nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \ |
43 | "fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \ | |
44 | bootm 400000 \0" \ | |
0608e04d | 45 | "panic_boot=echo No Bootdevice !!! reset\0" \ |
e604e409 | 46 | "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \ |
0608e04d | 47 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
e604e409 | 48 | "addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \ |
fe126d8b | 49 | ":${netmask}:${hostname}:${netdev}:off\0" \ |
e604e409 HS |
50 | "addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \ |
51 | hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \ | |
52 | "console=ttyCPM0,115200\0" \ | |
0608e04d | 53 | "netdev=eth0\0" \ |
e604e409 | 54 | "contrast=20\0" \ |
0608e04d | 55 | "silent=1\0" \ |
e604e409 | 56 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ |
0608e04d | 57 | "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ |
e604e409 | 58 | "update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \ |
02b11f8e | 59 | "cp.b 200000 40050000 14000\0" |
682011ff WD |
60 | |
61 | #define CONFIG_BOOTCOMMAND \ | |
e604e409 | 62 | "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot" |
56f94be3 | 63 | |
e604e409 | 64 | #define CONFIG_PREBOOT "setenv preboot; saveenv" |
56f94be3 | 65 | |
0608e04d WD |
66 | #define CONFIG_MISC_INIT_R 1 |
67 | #define CONFIG_MISC_INIT_F 1 | |
56f94be3 WD |
68 | |
69 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
e604e409 | 70 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
56f94be3 | 71 | |
02b11f8e | 72 | #define CONFIG_WATCHDOG 1 /* watchdog enabled */ |
56f94be3 | 73 | |
0608e04d | 74 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
56f94be3 WD |
75 | |
76 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
77 | ||
7be044e4 JL |
78 | /* |
79 | * BOOTP options | |
80 | */ | |
81 | #define CONFIG_BOOTP_SUBNETMASK | |
82 | #define CONFIG_BOOTP_GATEWAY | |
83 | #define CONFIG_BOOTP_HOSTNAME | |
84 | #define CONFIG_BOOTP_BOOTPATH | |
85 | #define CONFIG_BOOTP_BOOTFILESIZE | |
86 | ||
56f94be3 WD |
87 | #define CONFIG_MAC_PARTITION |
88 | #define CONFIG_DOS_PARTITION | |
89 | ||
02b11f8e WD |
90 | /* |
91 | * enable I2C and select the hardware/software driver | |
92 | */ | |
ea818dbb HS |
93 | #define CONFIG_SYS_I2C |
94 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
95 | #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ | |
96 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE | |
02b11f8e | 97 | |
02b11f8e WD |
98 | /* |
99 | * Software (bit-bang) I2C driver configuration | |
100 | */ | |
101 | #define PB_SCL 0x00000020 /* PB 26 */ | |
102 | #define PB_SDA 0x00000010 /* PB 27 */ | |
103 | ||
104 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
105 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
106 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
107 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
108 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
109 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
110 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
111 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
112 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ | |
02b11f8e | 113 | |
02b11f8e WD |
114 | /*----------------------------------------------------------------------- |
115 | * I2C Configuration | |
116 | */ | |
117 | ||
e604e409 HS |
118 | #define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ |
119 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ | |
0608e04d | 120 | |
02b11f8e WD |
121 | /* List of I2C addresses to be verified by POST */ |
122 | ||
60aaaa07 PT |
123 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \ |
124 | CONFIG_SYS_I2C_RTC_ADDR, \ | |
125 | } | |
02b11f8e | 126 | |
02b11f8e WD |
127 | #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ |
128 | ||
6d0f6bcf | 129 | #define CONFIG_SYS_DISCOVER_PHY |
63ff004c | 130 | #define CONFIG_MII |
02b11f8e | 131 | |
56f94be3 WD |
132 | /* Define to allow the user to overwrite serial and ethaddr */ |
133 | #define CONFIG_ENV_OVERWRITE | |
348f258f JL |
134 | |
135 | /* | |
136 | * Command line configuration. | |
137 | */ | |
138 | #include <config_cmd_default.h> | |
139 | ||
140 | #define CONFIG_CMD_DATE | |
141 | #define CONFIG_CMD_DHCP | |
142 | #define CONFIG_CMD_I2C | |
143 | #define CONFIG_CMD_IDE | |
e604e409 | 144 | #define CONFIG_CMD_MII |
348f258f | 145 | #define CONFIG_CMD_NFS |
e604e409 | 146 | #define CONFIG_CMD_FAT |
348f258f JL |
147 | #define CONFIG_CMD_SNTP |
148 | ||
af075ee9 JL |
149 | #ifdef CONFIG_POST |
150 | #define CONFIG_CMD_DIAG | |
151 | #endif | |
56f94be3 WD |
152 | |
153 | /* | |
154 | * Miscellaneous configurable options | |
155 | */ | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
157 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
348f258f | 158 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 159 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
56f94be3 | 160 | #else |
e604e409 | 161 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
56f94be3 | 162 | #endif |
e604e409 HS |
163 | /* Print Buffer Size */ |
164 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
166 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
56f94be3 | 167 | |
e604e409 HS |
168 | #define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ |
169 | #define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */ | |
170 | #define CONFIG_SYS_ALT_MEMTEST 1 | |
171 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */ | |
56f94be3 | 172 | |
e604e409 | 173 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
56f94be3 | 174 | |
e604e409 | 175 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
56f94be3 | 176 | |
6d0f6bcf | 177 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } |
56f94be3 | 178 | |
6d0f6bcf | 179 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 |
682011ff | 180 | |
56f94be3 WD |
181 | /* |
182 | * Low Level Configuration Settings | |
183 | * (address mappings, register initial values, etc.) | |
184 | * You should know what you are doing if you make changes here. | |
185 | */ | |
186 | /*----------------------------------------------------------------------- | |
187 | * Internal Memory Mapped Register | |
188 | */ | |
6d0f6bcf | 189 | #define CONFIG_SYS_IMMR 0xFFF00000 |
56f94be3 WD |
190 | |
191 | /*----------------------------------------------------------------------- | |
192 | * Definitions for initial stack pointer and data area (in DPRAM) | |
193 | */ | |
6d0f6bcf | 194 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 195 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 196 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 197 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
56f94be3 WD |
198 | |
199 | /*----------------------------------------------------------------------- | |
200 | * Start addresses for the final memory configuration | |
201 | * (Set up by the startup code) | |
6d0f6bcf | 202 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
56f94be3 | 203 | */ |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
205 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
206 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ | |
207 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
208 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
56f94be3 WD |
209 | |
210 | /* | |
211 | * For booting Linux, the board info and command line data | |
212 | * have to be in the first 8 MB of memory, since this is | |
213 | * the maximum mapped by the Linux kernel during initialization. | |
214 | */ | |
6d0f6bcf | 215 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
56f94be3 WD |
216 | |
217 | /*----------------------------------------------------------------------- | |
218 | * FLASH organization | |
219 | */ | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
221 | #define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ | |
56f94be3 | 222 | |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
224 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
56f94be3 | 225 | |
5a1aceb0 | 226 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
227 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
228 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ | |
229 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
56f94be3 | 230 | |
e604e409 HS |
231 | /*----------------------------------------------------------------------- |
232 | * Dynamic MTD partition support | |
233 | */ | |
234 | #define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \ | |
2d941de9 WD |
235 | "64k(env)," \ |
236 | "128k(splash)," \ | |
237 | "512k(etc)," \ | |
238 | "64k(hw-info)" | |
e604e409 | 239 | |
56f94be3 WD |
240 | /*----------------------------------------------------------------------- |
241 | * Hardware Information Block | |
242 | */ | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ |
244 | #define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */ | |
e604e409 HS |
245 | #define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */ |
246 | ||
56f94be3 WD |
247 | /*----------------------------------------------------------------------- |
248 | * Cache Configuration | |
249 | */ | |
6d0f6bcf | 250 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
348f258f | 251 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 252 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
56f94be3 WD |
253 | #endif |
254 | ||
255 | /*----------------------------------------------------------------------- | |
256 | * SYPCR - System Protection Control 11-9 | |
257 | * SYPCR can only be written once after reset! | |
258 | *----------------------------------------------------------------------- | |
259 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
260 | */ | |
6d0f6bcf | 261 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
56f94be3 WD |
262 | |
263 | /*----------------------------------------------------------------------- | |
264 | * SIUMCR - SIU Module Configuration 11-6 | |
265 | *----------------------------------------------------------------------- | |
266 | * PCMCIA config., multi-function pin tri-state | |
267 | */ | |
6d0f6bcf | 268 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) |
56f94be3 WD |
269 | |
270 | /*----------------------------------------------------------------------- | |
271 | * TBSCR - Time Base Status and Control 11-26 | |
272 | *----------------------------------------------------------------------- | |
273 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
274 | */ | |
6d0f6bcf | 275 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
56f94be3 WD |
276 | |
277 | /*----------------------------------------------------------------------- | |
278 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
279 | *----------------------------------------------------------------------- | |
280 | */ | |
6d0f6bcf | 281 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
56f94be3 WD |
282 | |
283 | /*----------------------------------------------------------------------- | |
284 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
285 | *----------------------------------------------------------------------- | |
286 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
287 | */ | |
6d0f6bcf | 288 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
56f94be3 WD |
289 | |
290 | /*----------------------------------------------------------------------- | |
291 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
292 | *----------------------------------------------------------------------- | |
293 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
294 | * interrupt status bit | |
295 | * | |
296 | * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! | |
297 | */ | |
6d0f6bcf | 298 | #define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) |
56f94be3 WD |
299 | |
300 | /*----------------------------------------------------------------------- | |
301 | * SCCR - System Clock and reset Control Register 15-27 | |
302 | *----------------------------------------------------------------------- | |
303 | * Set clock output, timebase and RTC source and divider, | |
304 | * power management and some other internal clocks | |
305 | */ | |
306 | #define SCCR_MASK SCCR_EBDF00 | |
6d0f6bcf | 307 | #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \ |
56f94be3 WD |
308 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
309 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
310 | SCCR_DFALCD00) | |
311 | ||
312 | /*----------------------------------------------------------------------- | |
313 | * PCMCIA stuff | |
314 | *----------------------------------------------------------------------- | |
315 | * | |
316 | */ | |
317 | ||
ea909b76 | 318 | /* KUP4K use both slots, SLOT_A as "primary". */ |
0608e04d | 319 | #define CONFIG_PCMCIA_SLOT_A 1 |
56f94be3 | 320 | |
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
322 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
323 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
324 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
325 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
326 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
327 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
328 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
56f94be3 | 329 | |
ea909b76 WD |
330 | #define PCMCIA_SOCKETS_NO 2 |
331 | #define PCMCIA_MEM_WIN_NO 8 | |
56f94be3 WD |
332 | /*----------------------------------------------------------------------- |
333 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
334 | *----------------------------------------------------------------------- | |
335 | */ | |
336 | ||
8d1165e1 | 337 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
0608e04d | 338 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
56f94be3 | 339 | |
0608e04d WD |
340 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
341 | #define CONFIG_IDE_LED 1 /* LED for ide supported */ | |
56f94be3 WD |
342 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
343 | ||
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_IDE_MAXBUS 2 |
345 | #define CONFIG_SYS_IDE_MAXDEVICE 4 | |
56f94be3 | 346 | |
6d0f6bcf | 347 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
56f94be3 | 348 | |
6d0f6bcf | 349 | #define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) |
ea909b76 | 350 | |
6d0f6bcf | 351 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
56f94be3 WD |
352 | |
353 | /* Offset for data I/O */ | |
6d0f6bcf | 354 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
56f94be3 WD |
355 | |
356 | /* Offset for normal register accesses */ | |
6d0f6bcf | 357 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
56f94be3 WD |
358 | |
359 | /* Offset for alternate registers */ | |
6d0f6bcf | 360 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
56f94be3 | 361 | |
56f94be3 WD |
362 | /*----------------------------------------------------------------------- |
363 | * | |
364 | *----------------------------------------------------------------------- | |
365 | * | |
366 | */ | |
6d0f6bcf | 367 | #define CONFIG_SYS_DER 0 |
56f94be3 WD |
368 | |
369 | /* | |
370 | * Init Memory Controller: | |
371 | * | |
372 | * BR0/1 and OR0/1 (FLASH) | |
373 | */ | |
374 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
375 | ||
376 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
377 | * restrict access enough to keep SRAM working (if any) | |
378 | * but not too much to meddle with FLASH accesses | |
379 | */ | |
6d0f6bcf JCPV |
380 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
381 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
56f94be3 WD |
382 | |
383 | /* | |
384 | * FLASH timing: | |
385 | */ | |
e604e409 HS |
386 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \ |
387 | OR_SCY_5_CLK | OR_EHTR | OR_BI) | |
56f94be3 | 388 | |
e604e409 HS |
389 | #define CONFIG_SYS_OR0_REMAP \ |
390 | (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
391 | #define CONFIG_SYS_OR0_PRELIM \ | |
392 | (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
393 | #define CONFIG_SYS_BR0_PRELIM \ | |
394 | ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) | |
56f94be3 WD |
395 | |
396 | ||
56f94be3 | 397 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
6d0f6bcf | 398 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
56f94be3 | 399 | |
56f94be3 WD |
400 | /* |
401 | * Memory Periodic Timer Prescaler | |
402 | * | |
403 | * The Divider for PTA (refresh timer) configuration is based on an | |
404 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
405 | * the number of chip selects (NCS) and the actually needed refresh | |
406 | * rate is done by setting MPTPR. | |
407 | * | |
408 | * PTA is calculated from | |
409 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
410 | * | |
411 | * gclk CPU clock (not bus clock!) | |
412 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
413 | * | |
0608e04d WD |
414 | * 4096 Rows from SDRAM example configuration |
415 | * 1000 factor s -> ms | |
416 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
417 | * 4 Number of refresh cycles per period | |
418 | * 64 Refresh cycle in ms per number of rows | |
56f94be3 WD |
419 | * -------------------------------------------- |
420 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
421 | * | |
422 | * 50 MHz => 50.000.000 / Divider = 98 | |
423 | * 66 Mhz => 66.000.000 / Divider = 129 | |
424 | * 80 Mhz => 80.000.000 / Divider = 156 | |
425 | */ | |
426 | #if defined(CONFIG_80MHz) | |
6d0f6bcf | 427 | #define CONFIG_SYS_MAMR_PTA 156 |
56f94be3 | 428 | #elif defined(CONFIG_66MHz) |
6d0f6bcf | 429 | #define CONFIG_SYS_MAMR_PTA 129 |
56f94be3 | 430 | #else /* 50 MHz */ |
6d0f6bcf | 431 | #define CONFIG_SYS_MAMR_PTA 98 |
56f94be3 WD |
432 | #endif /*CONFIG_??MHz */ |
433 | ||
434 | /* | |
435 | * For 16 MBit, refresh rates could be 31.3 us | |
436 | * (= 64 ms / 2K = 125 / quad bursts). | |
437 | * For a simpler initialization, 15.6 us is used instead. | |
438 | * | |
6d0f6bcf JCPV |
439 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
440 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
56f94be3 | 441 | */ |
6d0f6bcf | 442 | #define CONFIG_SYS_MPTPR 0x400 |
56f94be3 WD |
443 | |
444 | /* | |
445 | * MAMR settings for SDRAM | |
446 | */ | |
e604e409 HS |
447 | |
448 | /* 8 column SDRAM */ | |
449 | #define CONFIG_SYS_MAMR_8COL 0x68802114 | |
450 | /* 9 column SDRAM */ | |
451 | #define CONFIG_SYS_MAMR_9COL 0x68904114 | |
452 | ||
453 | /* | |
454 | * Chip Selects | |
455 | */ | |
456 | #define CONFIG_SYS_OR0 | |
457 | #define CONFIG_SYS_BR0 | |
458 | ||
459 | #define CONFIG_SYS_OR1_8COL 0xFF000A00 | |
460 | #define CONFIG_SYS_BR1_8COL 0x00000081 | |
461 | #define CONFIG_SYS_OR2_8COL 0xFE000A00 | |
462 | #define CONFIG_SYS_BR2_8COL 0x01000081 | |
463 | #define CONFIG_SYS_OR3_8COL 0xFC000A00 | |
464 | #define CONFIG_SYS_BR3_8COL 0x02000081 | |
465 | ||
466 | #define CONFIG_SYS_OR1_9COL 0xFE000A00 | |
467 | #define CONFIG_SYS_BR1_9COL 0x00000081 | |
468 | #define CONFIG_SYS_OR2_9COL 0xFE000A00 | |
469 | #define CONFIG_SYS_BR2_9COL 0x02000081 | |
470 | #define CONFIG_SYS_OR3_9COL 0xFE000A00 | |
471 | #define CONFIG_SYS_BR3_9COL 0x04000081 | |
472 | ||
473 | #define CONFIG_SYS_OR4 0xFFFF8926 | |
474 | #define CONFIG_SYS_BR4 0x90000401 | |
475 | ||
476 | #define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */ | |
477 | #define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */ | |
478 | ||
479 | #define LATCH_ADDR 0x90000200 | |
56f94be3 | 480 | |
56f94be3 | 481 | #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
e604e409 HS |
482 | #define CONFIG_AUTOBOOT_STOP_STR "." |
483 | #define CONFIG_SILENT_CONSOLE 1 | |
2d941de9 | 484 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ |
e604e409 | 485 | #define CONFIG_VERSION_VARIABLE 1 |
56f94be3 | 486 | |
8011ec63 HS |
487 | /* pass open firmware flat tree */ |
488 | #define CONFIG_OF_LIBFDT 1 | |
489 | #define CONFIG_OF_BOARD_SETUP 1 | |
490 | ||
56f94be3 | 491 | #endif /* __CONFIG_H */ |