[people/ms/u-boot.git] / include / configs / KUP4K.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 * Derived from ../tqm8xx/tqm8xx.c
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
#define CONFIG_KUP4K		1	/* ...on a KUP4K module */

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
#endif

#define CONFIG_BOARD_TYPES	1	/* support board types		*/


#undef	CONFIG_BOOTARGS


#define CONFIG_EXTRA_ENV_SETTINGS						\
"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
 "run addhw; diskboot 200000 0:1; bootm 200000\0"				\
"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
 "run addhw; diskboot 200000 2:1; bootm 200000\0"				\
"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0"			\
"panic_boot=echo No Bootdevice !!! reset\0"					\
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
"ramargs=setenv bootargs root=/dev/ram rw\0"					\
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}"	\
 ":${netmask}:${hostname}:${netdev}:off\0"					\
"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0"		\
"netdev=eth0\0"									\
"contrast=55\0"									\
"silent=1\0"									\
"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"		\
"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};"		\
 "cp.b 200000 40050000 14000\0"

#define CONFIG_BOOTCOMMAND  \
    "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"


#define CONFIG_MISC_INIT_R	1
#define CONFIG_MISC_INIT_F	1

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#define	CONFIG_WATCHDOG	1		/* watchdog enabled		*/

#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION


/*
 * enable I2C and select the hardware/software driver
 */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/

#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
#define CFG_I2C_SLAVE		0xFE

#ifdef CONFIG_SOFT_I2C
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
#endif	/* CONFIG_SOFT_I2C */


/*-----------------------------------------------------------------------
 * I2C Configuration
 */

#define CFG_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/


/* List of I2C addresses to be verified by POST */

#define I2C_ADDR_LIST	{CFG_I2C_PICIO_ADDR,	\
			CFG_I2C_RTC_ADDR,	\
			}


#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/

#define CFG_DISCOVER_PHY
#define CONFIG_MII

#if 0
#define CONFIG_ETHADDR                  00:0B:64:00:00:00 /* our OUI from IEEE */
#endif
#define CONFIG_KUP4K_LOGO               0x40050000  /* Address of logo bitmap */

/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#if 1
/* POST support */

#define CONFIG_POST		(CFG_POST_CPU	   | \
				 CFG_POST_RTC	   | \
				 CFG_POST_I2C)
#endif


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP

#ifdef CONFIG_POST
    #define CONFIG_CMD_DIAG
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x000400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x002C00000	/* 4 ... 44 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x200000	/* default load address */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }

#define CFG_CONSOLE_INFO_QUIET 1

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000
#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
#define CFG_ENV_SECT_SIZE	0x10000

/* Address and size of Redundant Environment Sector	*/
#if 0
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#if 1
#define CFG_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
#define CFG_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
#define CFG_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
#endif
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
#define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF00
#define CFG_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */

/* KUP4K use both slots, SLOT_A as "primary". */
#define CONFIG_PCMCIA_SLOT_A 1

#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

#define PCMCIA_SOCKETS_NO 2
#define PCMCIA_MEM_WIN_NO 8
/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#define CONFIG_IDE_LED		1	/* LED	 for ide supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		2
#define CFG_IDE_MAXDEVICE	4

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_IDE1_OFFSET	(4 * CFG_PCMCIA_MEM_SIZE)

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0100


/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */
#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_2_CLK | OR_EHTR | OR_BI)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )


/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	0x00000A00


/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096	 Rows from SDRAM example configuration
 * 1000	 factor s -> ms
 *   32	 PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4	 Number of refresh cycles per period
 *   64	 Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
#if   defined(CONFIG_80MHz)
#define CFG_MAMR_PTA		156
#elif defined(CONFIG_66MHz)
#define CFG_MAMR_PTA		129
#else		/*   50 MHz */
#define CFG_MAMR_PTA		 98
#endif	/*CONFIG_??MHz */

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CFG_MPTPR 0x400

/*
 * MAMR settings for SDRAM
 */
#define CFG_MAMR 0x80802114

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/


#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
#if 0
#define CONFIG_AUTOBOOT_PROMPT		"Boote in %d Sekunden - stop mit \"2\"\n"
#endif
#define CONFIG_AUTOBOOT_STOP_STR	"." /* easy to stop for now */
#define CONFIG_SILENT_CONSOLE	1

#endif	/* __CONFIG_H */
Commit	Line	Data
56f94be3	1	/*
414eec35	2	* (C) Copyright 2000-2005
56f94be3 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
0608e04d	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
56f94be3 WD	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* board/config.h - configuration options, board specific
	27	* Derived from ../tqm8xx/tqm8xx.c
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37
	38	#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
	39	#define CONFIG_KUP4K 1 /* ...on a KUP4K module */
	40
0608e04d	41	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
56f94be3 WD	42	#undef CONFIG_8xx_CONS_SMC2
56f94be3 WD	43	#undef CONFIG_8xx_CONS_NONE
682011ff	44	#define CONFIG_BAUDRATE 115200 /* console baudrate */
56f94be3 WD	45	#if 0
	46	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	47	#else
682011ff	48	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
56f94be3 WD	49	#endif
56f94be3 WD	50
56f94be3 WD	51	#define CONFIG_BOARD_TYPES 1 /* support board types */
56f94be3 WD	52
56f94be3 WD	53
	54	#undef CONFIG_BOOTARGS
	55
56f94be3	56
0608e04d WD	57	#define CONFIG_EXTRA_ENV_SETTINGS \
	58	"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
	59	"run addhw; diskboot 200000 0:1; bootm 200000\0" \
	60	"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \
	61	"run addhw; diskboot 200000 2:1; bootm 200000\0" \
	62	"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \
	63	"panic_boot=echo No Bootdevice !!! reset\0" \
fe126d8b	64	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
0608e04d	65	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	66	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
	67	":${netmask}:${hostname}:${netdev}:off\0" \
	68	"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
0608e04d WD	69	"netdev=eth0\0" \
	70	"contrast=55\0" \
	71	"silent=1\0" \
	72	"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
fe126d8b	73	"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \
02b11f8e	74	"cp.b 200000 40050000 14000\0"
682011ff WD	75
	76	#define CONFIG_BOOTCOMMAND \
	77	"run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
56f94be3	78
56f94be3	79
0608e04d WD	80	#define CONFIG_MISC_INIT_R 1
0608e04d WD	81	#define CONFIG_MISC_INIT_F 1
56f94be3 WD	82
	83	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	84	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	85
02b11f8e	86	#define CONFIG_WATCHDOG 1 /* watchdog enabled */
56f94be3	87
0608e04d	88	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
56f94be3 WD	89
	90	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	91
	92	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
	93
	94	#define CONFIG_MAC_PARTITION
	95	#define CONFIG_DOS_PARTITION
	96
56f94be3	97
02b11f8e WD	98	/*
	99	* enable I2C and select the hardware/software driver
	100	*/
	101	#undef CONFIG_HARD_I2C /* I2C with hardware support */
	102	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	103
	104	#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
	105	#define CFG_I2C_SLAVE 0xFE
	106
	107	#ifdef CONFIG_SOFT_I2C
	108	/*
	109	* Software (bit-bang) I2C driver configuration
	110	*/
	111	#define PB_SCL 0x00000020 /* PB 26 */
	112	#define PB_SDA 0x00000010 /* PB 27 */
	113
	114	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	115	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	116	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	117	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	118	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	119	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	120	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	121	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	122	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
	123	#endif /* CONFIG_SOFT_I2C */
	124
	125
	126	/*-----------------------------------------------------------------------
	127	* I2C Configuration
	128	*/
	129
	130	#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
	131	#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
	132
0608e04d	133
02b11f8e WD	134	/* List of I2C addresses to be verified by POST */
	135
	136	#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \
	137	CFG_I2C_RTC_ADDR, \
	138	}
	139
	140
	141	#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
	142
	143	#define CFG_DISCOVER_PHY
63ff004c	144	#define CONFIG_MII
02b11f8e WD	145
	146	#if 0
	147	#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
	148	#endif
	149	#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */
56f94be3 WD	150
	151	/* Define to allow the user to overwrite serial and ethaddr */
	152	#define CONFIG_ENV_OVERWRITE
02b11f8e WD	153	#if 1
	154	/* POST support */
	155
	156	#define CONFIG_POST (CFG_POST_CPU \| \
	157	CFG_POST_RTC \| \
	158	CFG_POST_I2C)
02b11f8e	159	#endif
56f94be3	160
348f258f JL	161
	162	/*
	163	* Command line configuration.
	164	*/
	165	#include <config_cmd_default.h>
	166
	167	#define CONFIG_CMD_DATE
	168	#define CONFIG_CMD_DHCP
	169	#define CONFIG_CMD_I2C
	170	#define CONFIG_CMD_IDE
	171	#define CONFIG_CMD_NFS
348f258f JL	172	#define CONFIG_CMD_SNTP
348f258f JL	173
af075ee9 JL	174	#ifdef CONFIG_POST
	175	#define CONFIG_CMD_DIAG
	176	#endif
56f94be3 WD	177
	178	/*
	179	* Miscellaneous configurable options
	180	*/
0608e04d WD	181	#define CFG_LONGHELP /* undef to save memory */
0608e04d WD	182	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
348f258f	183	#if defined(CONFIG_CMD_KGDB)
0608e04d	184	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
56f94be3	185	#else
0608e04d	186	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
56f94be3	187	#endif
0608e04d WD	188	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
0608e04d WD	189	#define CFG_MAXARGS 16 /* max number of command args */
56f94be3 WD	190	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
56f94be3 WD	191
0608e04d WD	192	#define CFG_MEMTEST_START 0x000400000 /* memtest works on */
0608e04d WD	193	#define CFG_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */
56f94be3	194
0608e04d	195	#define CFG_LOAD_ADDR 0x200000 /* default load address */
56f94be3	196
0608e04d	197	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
56f94be3	198
0608e04d	199	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
56f94be3	200
682011ff WD	201	#define CFG_CONSOLE_INFO_QUIET 1
682011ff WD	202
56f94be3 WD	203	/*
	204	* Low Level Configuration Settings
	205	* (address mappings, register initial values, etc.)
	206	* You should know what you are doing if you make changes here.
	207	*/
	208	/*-----------------------------------------------------------------------
	209	* Internal Memory Mapped Register
	210	*/
	211	#define CFG_IMMR 0xFFF00000
	212
	213	/*-----------------------------------------------------------------------
	214	* Definitions for initial stack pointer and data area (in DPRAM)
	215	*/
	216	#define CFG_INIT_RAM_ADDR CFG_IMMR
0608e04d WD	217	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
0608e04d WD	218	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
56f94be3	219	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
0608e04d	220	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
56f94be3 WD	221
	222	/*-----------------------------------------------------------------------
	223	* Start addresses for the final memory configuration
	224	* (Set up by the startup code)
	225	* Please note that CFG_SDRAM_BASE _must_ start at 0
	226	*/
0608e04d	227	#define CFG_SDRAM_BASE 0x00000000
56f94be3	228	#define CFG_FLASH_BASE 0x40000000
0608e04d	229	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
56f94be3	230	#define CFG_MONITOR_BASE CFG_FLASH_BASE
0608e04d	231	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
56f94be3 WD	232
	233	/*
	234	* For booting Linux, the board info and command line data
	235	* have to be in the first 8 MB of memory, since this is
	236	* the maximum mapped by the Linux kernel during initialization.
	237	*/
0608e04d	238	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
56f94be3 WD	239
	240	/*-----------------------------------------------------------------------
	241	* FLASH organization
	242	*/
	243	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
0608e04d	244	#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
56f94be3 WD	245
	246	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	247	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	248
0608e04d	249	#define CFG_ENV_IS_IN_FLASH 1
02b11f8e	250	#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
0608e04d WD	251	#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
0608e04d WD	252	#define CFG_ENV_SECT_SIZE 0x10000
56f94be3 WD	253
	254	/* Address and size of Redundant Environment Sector */
	255	#if 0
	256	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
	257	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	258	#endif
	259	/*-----------------------------------------------------------------------
	260	* Hardware Information Block
	261	*/
02b11f8e WD	262	#if 1
	263	#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
	264	#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */
	265	#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
56f94be3 WD	266	#endif
	267	/*-----------------------------------------------------------------------
	268	* Cache Configuration
	269	*/
	270	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
348f258f	271	#if defined(CONFIG_CMD_KGDB)
56f94be3 WD	272	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	273	#endif
	274
	275	/*-----------------------------------------------------------------------
	276	* SYPCR - System Protection Control 11-9
	277	* SYPCR can only be written once after reset!
	278	*-----------------------------------------------------------------------
	279	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	280	*/
02b11f8e	281	#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
56f94be3 WD	282	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	283	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	284	#else
	285	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	286	#endif
	287
	288	/*-----------------------------------------------------------------------
	289	* SIUMCR - SIU Module Configuration 11-6
	290	*-----------------------------------------------------------------------
	291	* PCMCIA config., multi-function pin tri-state
	292	*/
	293	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC00)
	294
	295	/*-----------------------------------------------------------------------
	296	* TBSCR - Time Base Status and Control 11-26
	297	*-----------------------------------------------------------------------
	298	* Clear Reference Interrupt Status, Timebase freezing enabled
	299	*/
	300	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	301
	302	/*-----------------------------------------------------------------------
	303	* RTCSC - Real-Time Clock Status and Control Register 11-27
	304	*-----------------------------------------------------------------------
	305	*/
	306	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
	307
	308	/*-----------------------------------------------------------------------
	309	* PISCR - Periodic Interrupt Status and Control 11-31
	310	*-----------------------------------------------------------------------
	311	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	312	*/
	313	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	314
	315	/*-----------------------------------------------------------------------
	316	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	317	*-----------------------------------------------------------------------
	318	* Reset PLL lock status sticky bit, timer expired status bit and timer
	319	* interrupt status bit
	320	*
	321	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	322	*/
682011ff	323	#define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_TMIST )
56f94be3 WD	324
	325	/*-----------------------------------------------------------------------
	326	* SCCR - System Clock and reset Control Register 15-27
	327	*-----------------------------------------------------------------------
	328	* Set clock output, timebase and RTC source and divider,
	329	* power management and some other internal clocks
	330	*/
	331	#define SCCR_MASK SCCR_EBDF00
682011ff	332	#define CFG_SCCR (SCCR_TBS \| SCCR_EBDF01 \| \
56f94be3 WD	333	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	334	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	335	SCCR_DFALCD00)
	336
	337	/*-----------------------------------------------------------------------
	338	* PCMCIA stuff
	339	*-----------------------------------------------------------------------
	340	*
	341	*/
	342
ea909b76	343	/* KUP4K use both slots, SLOT_A as "primary". */
0608e04d	344	#define CONFIG_PCMCIA_SLOT_A 1
56f94be3 WD	345
	346	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
	347	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
	348	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
	349	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
	350	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
	351	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	352	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
	353	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
	354
ea909b76 WD	355	#define PCMCIA_SOCKETS_NO 2
ea909b76 WD	356	#define PCMCIA_MEM_WIN_NO 8
56f94be3 WD	357	/*-----------------------------------------------------------------------
	358	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	359	*-----------------------------------------------------------------------
	360	*/
	361
0608e04d	362	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
56f94be3	363
0608e04d WD	364	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
0608e04d WD	365	#define CONFIG_IDE_LED 1 /* LED for ide supported */
56f94be3 WD	366	#undef CONFIG_IDE_RESET /* reset for ide not supported */
56f94be3 WD	367
ea909b76 WD	368	#define CFG_IDE_MAXBUS 2
ea909b76 WD	369	#define CFG_IDE_MAXDEVICE 4
56f94be3 WD	370
	371	#define CFG_ATA_IDE0_OFFSET 0x0000
	372
ea909b76 WD	373	#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE)
ea909b76 WD	374
56f94be3 WD	375	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
	376
	377	/* Offset for data I/O */
	378	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
	379
	380	/* Offset for normal register accesses */
	381	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
	382
	383	/* Offset for alternate registers */
	384	#define CFG_ATA_ALT_OFFSET 0x0100
	385
	386
	387	/*-----------------------------------------------------------------------
	388	*
	389	*-----------------------------------------------------------------------
	390	*
	391	*/
0608e04d	392	#define CFG_DER 0
56f94be3 WD	393
	394	/*
	395	* Init Memory Controller:
	396	*
	397	* BR0/1 and OR0/1 (FLASH)
	398	*/
	399	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	400
	401	/* used to re-map FLASH both when starting from SRAM or FLASH:
	402	* restrict access enough to keep SRAM working (if any)
	403	* but not too much to meddle with FLASH accesses
	404	*/
	405	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
	406	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
	407
	408	/*
	409	* FLASH timing:
	410	*/
	411	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
	412	OR_SCY_2_CLK \| OR_EHTR \| OR_BI)
	413
	414	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
	415	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	416	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
	417
	418
56f94be3 WD	419	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
	420	#define CFG_OR_TIMING_SDRAM 0x00000A00
	421
56f94be3 WD	422
	423	/*
	424	* Memory Periodic Timer Prescaler
	425	*
	426	* The Divider for PTA (refresh timer) configuration is based on an
	427	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	428	* the number of chip selects (NCS) and the actually needed refresh
	429	* rate is done by setting MPTPR.
	430	*
	431	* PTA is calculated from
	432	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	433	*
	434	* gclk CPU clock (not bus clock!)
	435	* Trefresh Refresh cycle * 4 (four word bursts used)
	436	*
0608e04d WD	437	* 4096 Rows from SDRAM example configuration
	438	* 1000 factor s -> ms
	439	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	440	* 4 Number of refresh cycles per period
	441	* 64 Refresh cycle in ms per number of rows
56f94be3 WD	442	* --------------------------------------------
	443	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	444	*
	445	* 50 MHz => 50.000.000 / Divider = 98
	446	* 66 Mhz => 66.000.000 / Divider = 129
	447	* 80 Mhz => 80.000.000 / Divider = 156
	448	*/
	449	#if defined(CONFIG_80MHz)
	450	#define CFG_MAMR_PTA 156
	451	#elif defined(CONFIG_66MHz)
	452	#define CFG_MAMR_PTA 129
	453	#else /* 50 MHz */
	454	#define CFG_MAMR_PTA 98
	455	#endif /CONFIG_??MHz /
	456
	457	/*
	458	* For 16 MBit, refresh rates could be 31.3 us
	459	* (= 64 ms / 2K = 125 / quad bursts).
	460	* For a simpler initialization, 15.6 us is used instead.
	461	*
	462	* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
	463	* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
	464	*/
	465	#define CFG_MPTPR 0x400
	466
	467	/*
	468	* MAMR settings for SDRAM
	469	*/
	470	#define CFG_MAMR 0x80802114
	471
	472	/*
	473	* Internal Definitions
	474	*
	475	* Boot Flags
	476	*/
0608e04d	477	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
56f94be3 WD	478	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	479
	480
	481	#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
	482	#if 0
	483	#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n"
	484	#endif
682011ff	485	#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
0608e04d	486	#define CONFIG_SILENT_CONSOLE 1
56f94be3 WD	487
56f94be3 WD	488	#endif /* __CONFIG_H */