[people/ms/u-boot.git] / include / configs / KUP4X.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 * Derived from ../tqm8xx/tqm8xx.c
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC859T		1	/* This is a MPC859T CPU	*/
#define CONFIG_KUP4X		1	/* ...on a KUP4X module		*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate		*/

#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_SYS_8XX_FACT		8	/* Multiply by 8	*/
#define CONFIG_SYS_8XX_XIN		16000000	/* 16 MHz in	*/


#define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT))

/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
/* in general, we always know this for FADS+new ADS anyway */
#define CONFIG_8xx_GCLK_FREQ	 MPC8XX_HZ


#undef	CONFIG_BOOTARGS


#define CONFIG_EXTRA_ENV_SETTINGS						\
"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
  "run addhw;diskboot 200000 0:1;bootm 200000\0"				\
"usb_boot=setenv bootargs root=/dev/sda2 ip=off;				\
 run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;			\
 usb stop; bootm 200000\0"							\
"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0"				\
"panic_boot=echo No Bootdevice !!! reset\0"					\
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
"ramargs=setenv bootargs root=/dev/ram rw\0"					\
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}"	\
 ":${netmask}:${hostname}:${netdev}:off\0"					\
"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0"		\
"netdev=eth0\0"									\
"silent=1\0"									\
"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0"		\
"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};"		\
 "cp.b 200000 40040000 14000\0"

#define CONFIG_BOOTCOMMAND  \
    "run usb_boot;run slot_a_boot;run nfs_boot;run panic_boot"


#define CONFIG_MISC_INIT_R	1
#define CONFIG_MISC_INIT_F	1

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/

#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/

#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/*
 * enable I2C and select the hardware/software driver
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */

#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE

/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
#endif	/* CONFIG_SYS_I2C_SOFT */


/*-----------------------------------------------------------------------
 * I2C Configuration
 */

#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander	*/
#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC			*/


/* List of I2C addresses to be verified by POST */

#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_PICIO_ADDR,	\
					 CONFIG_SYS_I2C_RTC_ADDR,	\
					}


#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/

#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_MII

#undef CONFIG_KUP4K_LOGO

/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE


/* POST support */
#define CONFIG_POST		(CONFIG_SYS_POST_CPU	   | \
				 CONFIG_SYS_POST_RTC	   | \
				 CONFIG_SYS_POST_I2C)


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

#ifdef CONFIG_POST
    #define CONFIG_CMD_DIAG
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x000400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x003C00000	/* 4 ... 60 MB in DRAM	*/
#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }

#define CONFIG_SYS_CONSOLE_INFO_QUIET 1

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	0x10000

/* Address and size of Redundant Environment Sector	*/
#if 0
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#if 1
#define CONFIG_SYS_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
#endif
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)


/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)


/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * set the PLL, the low-power modes and the reset control (15-29)
 */
#define CONFIG_SYS_PLPRCR	((CONFIG_SYS_8XX_FACT << PLPRCR_MFI_SHIFT) |	\
				PLPRCR_SPLSS | PLPRCR_TEXPS)


/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF00
#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */

/* KUP4K use both slots, SLOT_A as "primary". */
#define CONFIG_PCMCIA_SLOT_A 1

#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

#define PCMCIA_SOCKETS_NO 1
#define PCMCIA_MEM_WIN_NO 8
/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#define CONFIG_IDE_LED			1   /* LED   for ide supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_IDE1_OFFSET	(4 * CONFIG_SYS_PCMCIA_MEM_SIZE)

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100


/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */
#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_2_CLK | OR_EHTR | OR_BI)

#define CONFIG_SYS_OR0_REMAP \
		(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM \
		(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM \
		((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )


/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00


#define CONFIG_SYS_MPTPR 0x400

/*
 * MAMR settings for SDRAM
 */
#define CONFIG_SYS_MAMR 0x80802114


/*
 * Chip Selects
 */

#define CONFIG_SYS_OR4 0xFFFF8926
#define CONFIG_SYS_BR4 0x90000401

#define LATCH_ADDR 0x90000200

#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot	*/

#define CONFIG_AUTOBOOT_STOP_STR	"."	/* easy to stop for now		*/
#define CONFIG_SILENT_CONSOLE	1

#define CONFIG_USB_STORAGE	1
#define CONFIG_USB_SL811HS	1

#endif	/* __CONFIG_H */
Commit	Line	Data
0608e04d	1	/*
414eec35	2	* (C) Copyright 2000-2005
0608e04d WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
0608e04d WD	7	*/
	8
	9	/*
	10	* board/config.h - configuration options, board specific
	11	* Derived from ../tqm8xx/tqm8xx.c
	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
e604e409 HS	22	#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */
e604e409 HS	23	#define CONFIG_KUP4X 1 /* ...on a KUP4X module */
0608e04d	24
2ae18241 WD	25	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	26
e604e409	27	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
0608e04d WD	28	#undef CONFIG_8xx_CONS_SMC2
0608e04d WD	29	#undef CONFIG_8xx_CONS_NONE
e604e409	30	#define CONFIG_BAUDRATE 115200 /* console baudrate */
0608e04d	31
e604e409	32	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
0608e04d	33
e604e409 HS	34	#define CONFIG_BOARD_TYPES 1 /* support board types */
	35
	36	#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */
	37	#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */
0608e04d WD	38
0608e04d WD	39
6d0f6bcf	40	#define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT))
0608e04d WD	41
	42	/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
	43	/* in general, we always know this for FADS+new ADS anyway */
	44	#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
	45
	46
	47	#undef CONFIG_BOOTARGS
	48
	49
	50	#define CONFIG_EXTRA_ENV_SETTINGS \
	51	"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
	52	"run addhw;diskboot 200000 0:1;bootm 200000\0" \
e604e409 HS	53	"usb_boot=setenv bootargs root=/dev/sda2 ip=off; \
	54	run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1; \
	55	usb stop; bootm 200000\0" \
0608e04d WD	56	"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
0608e04d WD	57	"panic_boot=echo No Bootdevice !!! reset\0" \
fe126d8b	58	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
0608e04d	59	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	60	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
	61	":${netmask}:${hostname}:${netdev}:off\0" \
	62	"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
0608e04d WD	63	"netdev=eth0\0" \
	64	"silent=1\0" \
	65	"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
fe126d8b	66	"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \
0608e04d WD	67	"cp.b 200000 40040000 14000\0"
	68
	69	#define CONFIG_BOOTCOMMAND \
e604e409	70	"run usb_boot;run slot_a_boot;run nfs_boot;run panic_boot"
0608e04d WD	71
	72
	73	#define CONFIG_MISC_INIT_R 1
	74	#define CONFIG_MISC_INIT_F 1
	75
	76	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
e604e409	77	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
0608e04d	78
02b11f8e	79	#define CONFIG_WATCHDOG 1 /* watchdog enabled */
0608e04d WD	80
	81	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	82
	83	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	84
7be044e4 JL	85	/*
	86	* BOOTP options
	87	*/
	88	#define CONFIG_BOOTP_SUBNETMASK
	89	#define CONFIG_BOOTP_GATEWAY
	90	#define CONFIG_BOOTP_HOSTNAME
	91	#define CONFIG_BOOTP_BOOTPATH
	92	#define CONFIG_BOOTP_BOOTFILESIZE
	93
0608e04d WD	94
	95	#define CONFIG_MAC_PARTITION
	96	#define CONFIG_DOS_PARTITION
	97
02b11f8e WD	98	/*
	99	* enable I2C and select the hardware/software driver
	100	*/
ea818dbb HS	101	#define CONFIG_SYS_I2C
ea818dbb HS	102	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
02b11f8e	103
ea818dbb HS	104	#ifdef CONFIG_SYS_I2C_SOFT
	105	#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
	106	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
02b11f8e	107
02b11f8e WD	108	/*
	109	* Software (bit-bang) I2C driver configuration
	110	*/
	111	#define PB_SCL 0x00000020 /* PB 26 */
	112	#define PB_SDA 0x00000010 /* PB 27 */
	113
	114	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	115	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	116	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	117	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	118	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	119	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	120	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	121	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	122	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
ea818dbb	123	#endif /* CONFIG_SYS_I2C_SOFT */
02b11f8e WD	124
	125
	126	/*-----------------------------------------------------------------------
	127	* I2C Configuration
	128	*/
	129
e604e409 HS	130	#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
e604e409 HS	131	#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
02b11f8e WD	132
	133
	134	/* List of I2C addresses to be verified by POST */
0608e04d	135
60aaaa07 PT	136	#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
	137	CONFIG_SYS_I2C_RTC_ADDR, \
	138	}
02b11f8e WD	139
	140
	141	#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
	142
6d0f6bcf	143	#define CONFIG_SYS_DISCOVER_PHY
63ff004c	144	#define CONFIG_MII
02b11f8e	145
0608e04d WD	146	#undef CONFIG_KUP4K_LOGO
	147
	148	/* Define to allow the user to overwrite serial and ethaddr */
	149	#define CONFIG_ENV_OVERWRITE
	150
02b11f8e	151
02b11f8e	152	/* POST support */
6d0f6bcf JCPV	153	#define CONFIG_POST (CONFIG_SYS_POST_CPU \| \
	154	CONFIG_SYS_POST_RTC \| \
	155	CONFIG_SYS_POST_I2C)
02b11f8e	156
348f258f JL	157
	158	/*
	159	* Command line configuration.
	160	*/
	161	#include <config_cmd_default.h>
	162
	163	#define CONFIG_CMD_DATE
	164	#define CONFIG_CMD_DHCP
	165	#define CONFIG_CMD_FAT
	166	#define CONFIG_CMD_I2C
	167	#define CONFIG_CMD_IDE
	168	#define CONFIG_CMD_NFS
348f258f JL	169	#define CONFIG_CMD_SNTP
	170	#define CONFIG_CMD_USB
	171
af075ee9 JL	172	#ifdef CONFIG_POST
	173	#define CONFIG_CMD_DIAG
	174	#endif
0608e04d WD	175
	176	/*
	177	* Miscellaneous configurable options
	178	*/
6d0f6bcf	179	#define CONFIG_SYS_LONGHELP /* undef to save memory */
348f258f	180	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	181	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0608e04d	182	#else
6d0f6bcf	183	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0608e04d	184	#endif
6d0f6bcf JCPV	185	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	186	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	187	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0608e04d	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
	190	#define CONFIG_SYS_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */
	191	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
0608e04d	192
6d0f6bcf	193	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
0608e04d	194
6d0f6bcf	195	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
0608e04d WD	196
	197	/*
	198	* Low Level Configuration Settings
	199	* (address mappings, register initial values, etc.)
	200	* You should know what you are doing if you make changes here.
	201	*/
	202	/*-----------------------------------------------------------------------
	203	* Internal Memory Mapped Register
	204	*/
6d0f6bcf	205	#define CONFIG_SYS_IMMR 0xFFF00000
0608e04d WD	206
	207	/*-----------------------------------------------------------------------
	208	* Definitions for initial stack pointer and data area (in DPRAM)
	209	*/
6d0f6bcf	210	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	211	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	212	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	213	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0608e04d WD	214
	215	/*-----------------------------------------------------------------------
	216	* Start addresses for the final memory configuration
	217	* (Set up by the startup code)
6d0f6bcf	218	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0608e04d	219	*/
6d0f6bcf JCPV	220	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	221	#define CONFIG_SYS_FLASH_BASE 0x40000000
	222	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */
	223	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	224	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
0608e04d WD	225
	226	/*
	227	* For booting Linux, the board info and command line data
	228	* have to be in the first 8 MB of memory, since this is
	229	* the maximum mapped by the Linux kernel during initialization.
	230	*/
6d0f6bcf	231	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0608e04d WD	232
	233	/*-----------------------------------------------------------------------
	234	* FLASH organization
	235	*/
6d0f6bcf JCPV	236	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	237	#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
0608e04d	238
6d0f6bcf JCPV	239	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	240	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0608e04d	241
5a1aceb0	242	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	243	#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
	244	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
	245	#define CONFIG_ENV_SECT_SIZE 0x10000
0608e04d WD	246
	247	/* Address and size of Redundant Environment Sector */
	248	#if 0
0e8d1586 JCPV	249	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
0e8d1586 JCPV	250	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
0608e04d WD	251	#endif
	252	/*-----------------------------------------------------------------------
	253	* Hardware Information Block
	254	*/
02b11f8e	255	#if 1
6d0f6bcf JCPV	256	#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
	257	#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
	258	#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
0608e04d WD	259	#endif
	260	/*-----------------------------------------------------------------------
	261	* Cache Configuration
	262	*/
6d0f6bcf	263	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
348f258f	264	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	265	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
0608e04d WD	266	#endif
	267
	268	/*-----------------------------------------------------------------------
	269	* SYPCR - System Protection Control 11-9
	270	* SYPCR can only be written once after reset!
	271	*-----------------------------------------------------------------------
	272	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	273	*/
02b11f8e	274	#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
6d0f6bcf	275	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
0608e04d WD	276	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
0608e04d WD	277	#else
6d0f6bcf	278	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
0608e04d WD	279	#endif
	280
	281	/*-----------------------------------------------------------------------
	282	* SIUMCR - SIU Module Configuration 11-6
	283	*-----------------------------------------------------------------------
	284	* PCMCIA config., multi-function pin tri-state
	285	*/
6d0f6bcf	286	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC00)
0608e04d WD	287
	288	/*-----------------------------------------------------------------------
	289	* TBSCR - Time Base Status and Control 11-26
	290	*-----------------------------------------------------------------------
	291	* Clear Reference Interrupt Status, Timebase freezing enabled
	292	*/
6d0f6bcf	293	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
0608e04d WD	294
	295
	296	/*-----------------------------------------------------------------------
	297	* PISCR - Periodic Interrupt Status and Control 11-31
	298	*-----------------------------------------------------------------------
	299	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	300	*/
6d0f6bcf	301	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
0608e04d WD	302
	303
	304	/*-----------------------------------------------------------------------
	305	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	306	*-----------------------------------------------------------------------
	307	* set the PLL, the low-power modes and the reset control (15-29)
	308	*/
6d0f6bcf	309	#define CONFIG_SYS_PLPRCR ((CONFIG_SYS_8XX_FACT << PLPRCR_MFI_SHIFT) \| \
0608e04d WD	310	PLPRCR_SPLSS \| PLPRCR_TEXPS)
	311
	312
	313	/*-----------------------------------------------------------------------
	314	* SCCR - System Clock and reset Control Register 15-27
	315	*-----------------------------------------------------------------------
	316	* Set clock output, timebase and RTC source and divider,
	317	* power management and some other internal clocks
	318	*/
	319	#define SCCR_MASK SCCR_EBDF00
6d0f6bcf	320	#define CONFIG_SYS_SCCR (SCCR_TBS \| SCCR_EBDF01 \| \
0608e04d WD	321	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	322	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	323	SCCR_DFALCD00)
	324
	325	/*-----------------------------------------------------------------------
	326	* PCMCIA stuff
	327	*-----------------------------------------------------------------------
	328	*
	329	*/
	330
	331	/* KUP4K use both slots, SLOT_A as "primary". */
	332	#define CONFIG_PCMCIA_SLOT_A 1
	333
6d0f6bcf JCPV	334	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	335	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	336	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	337	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	338	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	339	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	340	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	341	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
0608e04d WD	342
	343	#define PCMCIA_SOCKETS_NO 1
	344	#define PCMCIA_MEM_WIN_NO 8
	345	/*-----------------------------------------------------------------------
	346	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	347	*-----------------------------------------------------------------------
	348	*/
	349
8d1165e1	350	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
0608e04d WD	351	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	352
	353	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	354	#define CONFIG_IDE_LED 1 /* LED for ide supported */
	355	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	356
6d0f6bcf JCPV	357	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	358	#define CONFIG_SYS_IDE_MAXDEVICE 2
0608e04d	359
6d0f6bcf	360	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
0608e04d	361
6d0f6bcf	362	#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
0608e04d	363
6d0f6bcf	364	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
0608e04d WD	365
0608e04d WD	366	/* Offset for data I/O */
6d0f6bcf	367	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
0608e04d WD	368
0608e04d WD	369	/* Offset for normal register accesses */
6d0f6bcf	370	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
0608e04d WD	371
0608e04d WD	372	/* Offset for alternate registers */
6d0f6bcf	373	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
0608e04d WD	374
	375
	376	/*-----------------------------------------------------------------------
	377	*
	378	*-----------------------------------------------------------------------
	379	*
	380	*/
6d0f6bcf	381	#define CONFIG_SYS_DER 0
0608e04d WD	382
	383	/*
	384	* Init Memory Controller:
	385	*
	386	* BR0/1 and OR0/1 (FLASH)
	387	*/
	388	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	389
	390	/* used to re-map FLASH both when starting from SRAM or FLASH:
	391	* restrict access enough to keep SRAM working (if any)
	392	* but not too much to meddle with FLASH accesses
	393	*/
6d0f6bcf JCPV	394	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	395	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
0608e04d WD	396
	397	/*
	398	* FLASH timing:
	399	*/
6d0f6bcf	400	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
0608e04d WD	401	OR_SCY_2_CLK \| OR_EHTR \| OR_BI)
0608e04d WD	402
e604e409 HS	403	#define CONFIG_SYS_OR0_REMAP \
	404	(CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	405	#define CONFIG_SYS_OR0_PRELIM \
	406	(CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	407	#define CONFIG_SYS_BR0_PRELIM \
	408	((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
0608e04d WD	409
	410
	411	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	412	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
0608e04d WD	413
0608e04d WD	414
6d0f6bcf	415	#define CONFIG_SYS_MPTPR 0x400
0608e04d WD	416
	417	/*
	418	* MAMR settings for SDRAM
	419	*/
6d0f6bcf	420	#define CONFIG_SYS_MAMR 0x80802114
0608e04d WD	421
0608e04d WD	422
e604e409 HS	423	/*
	424	* Chip Selects
	425	*/
	426
	427	#define CONFIG_SYS_OR4 0xFFFF8926
	428	#define CONFIG_SYS_BR4 0x90000401
	429
	430	#define LATCH_ADDR 0x90000200
	431
0608e04d	432	#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
e604e409	433
0608e04d WD	434	#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
	435	#define CONFIG_SILENT_CONSOLE 1
	436
5cf91d6b WD	437	#define CONFIG_USB_STORAGE 1
	438	#define CONFIG_USB_SL811HS 1
	439
0608e04d	440	#endif /* __CONFIG_H */