[people/ms/u-boot.git] / include / configs / LANTEC.h

/*
 * (C) Copyright 2000, 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * (C) Copyright 2001
 * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
 * Bruno Achauer, Exet AG, bruno@exet-ag.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 * [derived from config_TQM850L.h]
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_LANTEC		2	/* ...on a Lantec rev.2 board	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

/*
 *  Port assignments (CONFIG_LANTEC == 1):
 *  - SMC1: J11 (MDB) ?
 *  - SMC2: J6  (Feature connector)
 *  - SCC2: J9  (RJ45)
 *  - SCC3: J8  (Sub-D9)
 *
 *  Port assignments (CONFIG_LANTEC == 2): TBD
 */


#undef CONFIG_8xx_CONS_SMC2           /* Console is on SMC2           */
#define	CONFIG_8xx_CONS_SCC3
#undef  CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE         38400   /* console baudrate = 38.4kbps  */
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CDP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_PING
#define CONFIG_CMD_PORTIO
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP

#undef CONFIG_CMD_XIMG

#if !(CONFIG_LANTEC >= 2)
    #undef CONFIG_CMD_DATE
    #undef CONFIG_CMD_NET
#endif


#if CONFIG_LANTEC >= 2
#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
#endif

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)

/*-----------------------------------------------------------------------
 * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
 *-----------------------------------------------------------------------
 */
#define	CONFIG_8xx_GCLK_FREQ	33000000

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
			/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
			/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/5 and OR0/5 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE5_PRELIM	0x60000000	/* FLASH bank #1	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing */
#define CONFIG_SYS_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | \
				 OR_SCY_5_CLK | OR_TRLX)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CONFIG_SYS_OR5_REMAP   CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR5_PRELIM  ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank #0        */
#define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */

/* SDRAM timing: Multiplexed addresses					*/
#define CONFIG_SYS_OR_TIMING_SDRAM     (OR_CSNT_SAM)

#define CONFIG_SYS_OR3_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * Memory Periodic Timer Prescaler
 */

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */
/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL \
			((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		""
#define MTDPARTS_DEFAULT	""
*/

#endif	/* __CONFIG_H */
Commit	Line	Data
8966f337 WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* (C) Copyright 2001
	5	* Torsten Stevens, FHG IMS, stevens@ims.fhg.de
	6	* Bruno Achauer, Exet AG, bruno@exet-ag.de.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/*
	28	* board/config.h - configuration options, board specific
	29	* [derived from config_TQM850L.h]
	30	*/
	31
	32	#ifndef __CONFIG_H
	33	#define __CONFIG_H
	34
	35	/*
	36	* High Level Configuration Options
	37	* (easy to change)
	38	*/
	39
	40	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	41	#define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */
	42
2ae18241 WD	43	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	44
8966f337 WD	45	/*
	46	* Port assignments (CONFIG_LANTEC == 1):
	47	* - SMC1: J11 (MDB) ?
	48	* - SMC2: J6 (Feature connector)
	49	* - SCC2: J9 (RJ45)
	50	* - SCC3: J8 (Sub-D9)
	51	*
	52	* Port assignments (CONFIG_LANTEC == 2): TBD
	53	*/
	54
	55
	56	#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */
	57	#define CONFIG_8xx_CONS_SCC3
	58	#undef CONFIG_8xx_CONS_NONE
	59	#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
	60	#if 0
	61	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	62	#else
	63	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	64	#endif
	65
	66	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	67
	68	#undef CONFIG_BOOTARGS
	69	#define CONFIG_BOOTCOMMAND \
	70	"setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"
	71
	72	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	73	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
8966f337 WD	74
	75	#undef CONFIG_WATCHDOG /* watchdog disabled */
	76
	77	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	78
7be044e4 JL	79	/*
	80	* BOOTP options
	81	*/
	82	#define CONFIG_BOOTP_SUBNETMASK
	83	#define CONFIG_BOOTP_GATEWAY
	84	#define CONFIG_BOOTP_HOSTNAME
	85	#define CONFIG_BOOTP_BOOTPATH
	86	#define CONFIG_BOOTP_BOOTFILESIZE
8966f337	87
8966f337	88
348f258f JL	89	/*
	90	* Command line configuration.
	91	*/
4e620410 JCPV	92	#include <config_cmd_default.h>
	93
	94	#define CONFIG_CMD_ASKENV
	95	#define CONFIG_CMD_CACHE
	96	#define CONFIG_CMD_CDP
	97	#define CONFIG_CMD_DATE
	98	#define CONFIG_CMD_DHCP
	99	#define CONFIG_CMD_DIAG
	100	#define CONFIG_CMD_FAT
	101	#define CONFIG_CMD_IMMAP
	102	#define CONFIG_CMD_PING
	103	#define CONFIG_CMD_PORTIO
	104	#define CONFIG_CMD_REGINFO
	105	#define CONFIG_CMD_SAVES
	106	#define CONFIG_CMD_SDRAM
	107	#define CONFIG_CMD_SNTP
	108
348f258f JL	109	#undef CONFIG_CMD_XIMG
	110
	111	#if !(CONFIG_LANTEC >= 2)
	112	#undef CONFIG_CMD_DATE
	113	#undef CONFIG_CMD_NET
8966f337 WD	114	#endif
8966f337 WD	115
348f258f	116
8966f337	117	#if CONFIG_LANTEC >= 2
348f258f	118	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
8966f337 WD	119	#endif
8966f337 WD	120
8966f337 WD	121	/*
	122	* Miscellaneous configurable options
	123	*/
6d0f6bcf JCPV	124	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	125	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
348f258f	126	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	127	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
8966f337	128	#else
6d0f6bcf	129	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
8966f337	130	#endif
6d0f6bcf JCPV	131	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	132	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	133	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
8966f337	134
6d0f6bcf JCPV	135	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	136	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
8966f337	137
6d0f6bcf	138	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
8966f337	139
6d0f6bcf	140	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
8966f337	141
6d0f6bcf	142	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
8966f337 WD	143
	144	/*
	145	* Low Level Configuration Settings
	146	* (address mappings, register initial values, etc.)
	147	* You should know what you are doing if you make changes here.
	148	*/
	149	/*-----------------------------------------------------------------------
	150	* Internal Memory Mapped Register
	151	*/
6d0f6bcf	152	#define CONFIG_SYS_IMMR 0xFFF00000
8966f337 WD	153
	154	/*-----------------------------------------------------------------------
	155	* Definitions for initial stack pointer and data area (in DPRAM)
	156	*/
6d0f6bcf	157	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	158	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
6d0f6bcf	159	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
553f0982	160	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf	161	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
8966f337 WD	162
	163	/*-----------------------------------------------------------------------
	164	* Start addresses for the final memory configuration
	165	* (Set up by the startup code)
6d0f6bcf	166	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
8966f337	167	*/
6d0f6bcf JCPV	168	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	169	#define CONFIG_SYS_FLASH_BASE 0x40000000
	170	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	171	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	172	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
8966f337 WD	173
	174	/*
	175	* For booting Linux, the board info and command line data
	176	* have to be in the first 8 MB of memory, since this is
	177	* the maximum mapped by the Linux kernel during initialization.
	178	*/
6d0f6bcf	179	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
8966f337 WD	180
	181	/*-----------------------------------------------------------------------
	182	* FLASH organization
	183	*/
6d0f6bcf JCPV	184	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	185	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
8966f337	186
6d0f6bcf JCPV	187	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	188	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
8966f337	189
5a1aceb0	190	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	191	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	192	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
8966f337 WD	193
	194	/*-----------------------------------------------------------------------
	195	* Cache Configuration
	196	*/
6d0f6bcf	197	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
348f258f	198	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	199	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
8966f337 WD	200	#endif
	201
	202	/*-----------------------------------------------------------------------
	203	* SYPCR - System Protection Control 11-9
	204	* SYPCR can only be written once after reset!
	205	*-----------------------------------------------------------------------
	206	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	207	*/
	208	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	209	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
8966f337 WD	210	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
8966f337 WD	211	#else
6d0f6bcf	212	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
8966f337 WD	213	#endif
	214
	215	/*-----------------------------------------------------------------------
	216	* SIUMCR - SIU Module Configuration 11-6
	217	*-----------------------------------------------------------------------
	218	* PCMCIA config., multi-function pin tri-state
	219	*/
6d0f6bcf	220	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01 \| SIUMCR_DLK)
8966f337 WD	221
	222	/*-----------------------------------------------------------------------
	223	* Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
	224	*-----------------------------------------------------------------------
	225	*/
	226	#define CONFIG_8xx_GCLK_FREQ 33000000
	227
	228	/*-----------------------------------------------------------------------
	229	* TBSCR - Time Base Status and Control 11-26
	230	*-----------------------------------------------------------------------
	231	* Clear Reference Interrupt Status, Timebase freezing enabled
	232	*/
6d0f6bcf	233	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
8966f337 WD	234
	235	/*-----------------------------------------------------------------------
	236	* RTCSC - Real-Time Clock Status and Control Register 11-27
	237	*-----------------------------------------------------------------------
	238	*/
6d0f6bcf	239	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
8966f337 WD	240
	241	/*-----------------------------------------------------------------------
	242	* PISCR - Periodic Interrupt Status and Control 11-31
	243	*-----------------------------------------------------------------------
	244	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	245	*/
6d0f6bcf	246	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
8966f337 WD	247
	248	/*-----------------------------------------------------------------------
	249	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	250	*-----------------------------------------------------------------------
	251	* Reset PLL lock status sticky bit, timer expired status bit and timer
	252	* interrupt status bit
	253	*
	254	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	255	*/
	256	/* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	257	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
8966f337 WD	258
	259	/*-----------------------------------------------------------------------
	260	* SCCR - System Clock and reset Control Register 15-27
	261	*-----------------------------------------------------------------------
	262	* Set clock output, timebase and RTC source and divider,
	263	* power management and some other internal clocks
	264	*/
	265	#define SCCR_MASK SCCR_EBDF11
	266	/* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	267	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
8966f337 WD	268	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	269	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	270	SCCR_DFALCD00)
	271
	272	/*-----------------------------------------------------------------------
	273	*
	274	*-----------------------------------------------------------------------
	275	*
	276	*/
6d0f6bcf	277	#define CONFIG_SYS_DER 0
8966f337 WD	278
	279	/*
	280	* Init Memory Controller:
	281	*
	282	* BR0/5 and OR0/5 (FLASH)
	283	*/
	284
	285	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	286	#define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */
	287
	288	/* used to re-map FLASH both when starting from SRAM or FLASH:
	289	* restrict access enough to keep SRAM working (if any)
	290	* but not too much to meddle with FLASH accesses
	291	*/
6d0f6bcf JCPV	292	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	293	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
8966f337 WD	294
8966f337 WD	295	/* FLASH timing */
6d0f6bcf	296	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_BI \| \
8bde7f77	297	OR_SCY_5_CLK \| OR_TRLX)
8966f337	298
6d0f6bcf JCPV	299	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	300	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	301	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
8966f337	302
6d0f6bcf JCPV	303	#define CONFIG_SYS_OR5_REMAP CONFIG_SYS_OR0_REMAP
	304	#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_OR0_PRELIM
	305	#define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) \| BR_V )
8966f337 WD	306
	307	/*
	308	* BR2/3 and OR2/3 (SDRAM)
	309	*
	310	*/
	311	#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
	312	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	313
	314	/* SDRAM timing: Multiplexed addresses */
6d0f6bcf	315	#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM)
8966f337	316
6d0f6bcf JCPV	317	#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	318	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
8966f337 WD	319
	320	/*
	321	* Memory Periodic Timer Prescaler
	322	*/
	323
	324	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	325	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	326	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
8966f337 WD	327
8966f337 WD	328	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	329	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	330	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
8966f337 WD	331
	332	/*
	333	* MAMR settings for SDRAM
	334	*/
	335	/* periodic timer for refresh */
6d0f6bcf	336	#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
8966f337 WD	337
8966f337 WD	338	/* 8 column SDRAM */
6d0f6bcf JCPV	339	#define CONFIG_SYS_MAMR_8COL \
6d0f6bcf JCPV	340	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
8966f337 WD	341	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	342	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	343
700a0c64 WD	344	/*
	345	* JFFS2 partitions
	346	*
	347	*/
	348	/* No command line, one static partition, whole device */
68d7d651	349	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	350	#define CONFIG_JFFS2_DEV "nor0"
	351	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	352	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	353
	354	/* mtdparts command line support */
	355	/*
68d7d651	356	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	357	#define MTDIDS_DEFAULT ""
	358	#define MTDPARTS_DEFAULT ""
	359	*/
	360
8966f337	361	#endif /* __CONFIG_H */