]>
Commit | Line | Data |
---|---|---|
bf9a5215 TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF5208EVBe. | |
3 | * | |
4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef _M5208EVBE_H | |
27 | #define _M5208EVBE_H | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | * (easy to change) | |
32 | */ | |
33 | #define CONFIG_MCF520x /* define processor family */ | |
34 | #define CONFIG_M5208 /* define processor type */ | |
35 | ||
36 | #define CONFIG_MCFUART | |
37 | #define CONFIG_SYS_UART_PORT (0) | |
38 | #define CONFIG_BAUDRATE 115200 | |
39 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } | |
40 | ||
41 | #undef CONFIG_WATCHDOG | |
42 | #define CONFIG_WATCHDOG_TIMEOUT 5000 | |
43 | ||
44 | /* Command line configuration */ | |
45 | #include <config_cmd_default.h> | |
46 | ||
47 | #define CONFIG_CMD_CACHE | |
48 | #define CONFIG_CMD_ELF | |
49 | #define CONFIG_CMD_FLASH | |
50 | #undef CONFIG_CMD_I2C | |
51 | #define CONFIG_CMD_MEMORY | |
52 | #define CONFIG_CMD_MISC | |
53 | #define CONFIG_CMD_MII | |
54 | #define CONFIG_CMD_NET | |
55 | #define CONFIG_CMD_PING | |
56 | #define CONFIG_CMD_REGINFO | |
57 | ||
58 | #define CONFIG_MCFFEC | |
59 | #ifdef CONFIG_MCFFEC | |
60 | # define CONFIG_NET_MULTI 1 | |
61 | # define CONFIG_MII 1 | |
62 | # define CONFIG_MII_INIT 1 | |
63 | # define CONFIG_SYS_DISCOVER_PHY | |
64 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
65 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
66 | # define CONFIG_HAS_ETH1 | |
67 | ||
68 | # define CONFIG_SYS_FEC0_PINMUX 0 | |
69 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
70 | # define MCFFEC_TOUT_LOOP 50000 | |
71 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ | |
72 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
73 | # define FECDUPLEX FULL | |
74 | # define FECSPEED _100BASET | |
75 | # else | |
76 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
77 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
78 | # endif | |
79 | # endif /* CONFIG_SYS_DISCOVER_PHY */ | |
80 | #endif | |
81 | ||
82 | /* Timer */ | |
83 | #define CONFIG_MCFTMR | |
84 | #undef CONFIG_MCFPIT | |
85 | ||
86 | /* I2C */ | |
87 | #define CONFIG_FSL_I2C | |
88 | #define CONFIG_HARD_I2C /* I2C with hw support */ | |
89 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
90 | #define CONFIG_SYS_I2C_SPEED 80000 | |
91 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
92 | #define CONFIG_SYS_I2C_OFFSET 0x58000 | |
93 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR | |
94 | ||
95 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
96 | #define CONFIG_UDP_CHECKSUM | |
97 | ||
98 | #ifdef CONFIG_MCFFEC | |
99 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 | |
100 | # define CONFIG_IPADDR 192.162.1.2 | |
101 | # define CONFIG_NETMASK 255.255.255.0 | |
102 | # define CONFIG_SERVERIP 192.162.1.1 | |
103 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
104 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
105 | #endif /* CONFIG_MCFFEC */ | |
106 | ||
107 | #define CONFIG_HOSTNAME M5208EVBe | |
108 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
109 | "netdev=eth0\0" \ | |
110 | "loadaddr=40010000\0" \ | |
111 | "u-boot=u-boot.bin\0" \ | |
112 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
113 | "upd=run load; run prog\0" \ | |
114 | "prog=prot off 0 3ffff;" \ | |
115 | "era 0 3ffff;" \ | |
116 | "cp.b ${loadaddr} 0 ${filesize};" \ | |
117 | "save\0" \ | |
118 | "" | |
119 | ||
120 | #define CONFIG_PRAM 512 /* 512 KB */ | |
121 | #define CONFIG_SYS_PROMPT "-> " | |
122 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
123 | ||
124 | #ifdef CONFIG_CMD_KGDB | |
125 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
126 | #else | |
127 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
128 | #endif | |
129 | ||
130 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
131 | #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ | |
132 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ | |
133 | #define CONFIG_SYS_LOAD_ADDR 0x40010000 | |
134 | ||
135 | #define CONFIG_SYS_HZ 1000 | |
136 | #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ | |
137 | #define CONFIG_SYS_PLL_ODR 0x36 | |
138 | #define CONFIG_SYS_PLL_FDR 0x7D | |
139 | ||
140 | #define CONFIG_SYS_MBAR 0xFC000000 | |
141 | ||
142 | /* | |
143 | * Low Level Configuration Settings | |
144 | * (address mappings, register initial values, etc.) | |
145 | * You should know what you are doing if you make changes here. | |
146 | */ | |
147 | /* Definitions for initial stack pointer and data area (in DPRAM) */ | |
148 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 | |
553f0982 | 149 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ |
bf9a5215 | 150 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 151 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
bf9a5215 TL |
152 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
153 | ||
154 | /* | |
155 | * Start addresses for the final memory configuration | |
156 | * (Set up by the startup code) | |
157 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
158 | */ | |
159 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
f628e2f7 | 160 | #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ |
bf9a5215 TL |
161 | #define CONFIG_SYS_SDRAM_CFG1 0x43711630 |
162 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
163 | #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 | |
164 | #define CONFIG_SYS_SDRAM_EMOD 0x80010000 | |
165 | #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 | |
166 | ||
167 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
168 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
169 | ||
170 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
171 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
172 | ||
173 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
174 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
175 | ||
176 | /* | |
177 | * For booting Linux, the board info and command line data | |
178 | * have to be in the first 8 MB of memory, since this is | |
179 | * the maximum mapped by the Linux kernel during initialization ?? | |
180 | */ | |
181 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) | |
182 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) | |
183 | ||
184 | /* FLASH organization */ | |
185 | #define CONFIG_SYS_FLASH_CFI | |
186 | #ifdef CONFIG_SYS_FLASH_CFI | |
187 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
188 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ | |
189 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
190 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
191 | # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ | |
192 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
193 | #endif | |
194 | ||
195 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
196 | ||
197 | /* | |
198 | * Configuration for environment | |
199 | * Environment is embedded in u-boot in the second sector of the flash | |
200 | */ | |
201 | #define CONFIG_ENV_OFFSET 0x2000 | |
202 | #define CONFIG_ENV_SIZE 0x1000 | |
203 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
204 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
205 | ||
206 | /* Cache Configuration */ | |
207 | #define CONFIG_SYS_CACHELINE_SIZE 16 | |
208 | ||
dd9f054e | 209 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 210 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 211 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 212 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
213 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
214 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
215 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
216 | CF_ACR_EN | CF_ACR_SM_ALL) | |
217 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
218 | CF_CACR_DISD | CF_CACR_INVI | \ | |
219 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
220 | CF_CACR_EUSP) | |
221 | ||
bf9a5215 TL |
222 | /* Chipselect bank definitions */ |
223 | /* | |
224 | * CS0 - NOR Flash | |
225 | * CS1 - Available | |
226 | * CS2 - Available | |
227 | * CS3 - Available | |
228 | * CS4 - Available | |
229 | * CS5 - Available | |
230 | */ | |
231 | #define CONFIG_SYS_CS0_BASE 0 | |
232 | #define CONFIG_SYS_CS0_MASK 0x007F0001 | |
233 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
234 | ||
235 | #endif /* _M5208EVBE_H */ |