[thirdparty/u-boot.git] / include / configs / M52277EVB.h

/*
 * Configuation settings for the Freescale MCF52277 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M52277EVB_H
#define _M52277EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_HOSTNAME			M52277EVB
#define CONFIG_SYS_UBOOT_END		0x3FFFF
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate};"	\
	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	"updsbf=run loadsbf; run progsbf\0"	\
	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"progsbf=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	""
#endif

/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_SPLASH_SCREEN
#define CONFIG_LCD_LOGO
#define CONFIG_SHARP_LQ035Q7DH06
#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_SYS_USB_EHCI_REGS_BASE	0xFC0B0000
#define CONFIG_SYS_USB_EHCI_CPU_INIT
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x7
#ifdef CONFIG_CMD_SPI
#	define CONFIG_SYS_DSPI_CS2

#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#endif

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_SYS_INPUT_CLKSRC	16000000

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x81810000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*
 * Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_SPI_CS	2
#endif
#define CONFIG_ENV_OVERWRITE		1

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_OFFSET	0x30000
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x8000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_FLASH_SPANSION_S29WS_N	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
#endif

#define LDS_BOARD_TEXT \
        arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
	arch/m68k/lib/built-in.o            (.text*)

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x40000)
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

#ifdef CONFIG_CF_SBF
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#else
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#endif

#endif				/* _M52277EVB_H */
Commit	Line	Data
1552af70 TL	1	/*
	2	* Configuation settings for the Freescale MCF52277 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
1552af70 TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M52277EVB_H
	15	#define _M52277EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
1552af70	21
1552af70	22	#define CONFIG_MCFUART
6d0f6bcf	23	#define CONFIG_SYS_UART_PORT (0)
1552af70 TL	24
	25	#undef CONFIG_WATCHDOG
	26
	27	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	28
	29	/*
	30	* BOOTP options
	31	*/
	32	#define CONFIG_BOOTP_BOOTFILESIZE
1552af70	33
a21d0c2c TL	34	#define CONFIG_HOSTNAME M52277EVB
	35	#define CONFIG_SYS_UBOOT_END 0x3FFFF
	36	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
	37	#ifdef CONFIG_SYS_STMICRO_BOOT
	38	/* ST Micro serial flash */
1552af70	39	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d	40	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	41	"loadaddr=0x40010000\0" \
	42	"uboot=u-boot.bin\0" \
	43	"load=loadb ${loadaddr} ${baudrate};" \
5368c55d	44	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
1552af70	45	"upd=run load; run prog\0" \
a21d0c2c TL	46	"prog=sf probe 0:2 10000 1;" \
	47	"sf erase 0 30000;" \
	48	"sf write ${loadaddr} 0 30000;" \
1552af70 TL	49	"save\0" \
1552af70 TL	50	""
a21d0c2c TL	51	#endif
	52	#ifdef CONFIG_SYS_SPANSION_BOOT
	53	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d	54	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	55	"loadaddr=0x40010000\0" \
	56	"uboot=u-boot.bin\0" \
	57	"load=loadb ${loadaddr} ${baudrate}\0" \
	58	"upd=run load; run prog\0" \
5368c55d MV	59	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
	60	" " __stringify(CONFIG_SYS_UBOOT_END) ";" \
	61	"era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
	62	__stringify(CONFIG_SYS_UBOOT_END) ";" \
	63	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
a21d0c2c TL	64	" ${filesize}; save\0" \
	65	"updsbf=run loadsbf; run progsbf\0" \
	66	"loadsbf=loadb ${loadaddr} ${baudrate};" \
5368c55d	67	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
a21d0c2c TL	68	"progsbf=sf probe 0:2 10000 1;" \
	69	"sf erase 0 30000;" \
	70	"sf write ${loadaddr} 0 30000;" \
	71	""
	72	#endif
1552af70 TL	73
	74	/* LCD */
	75	#ifdef CONFIG_CMD_BMP
1552af70 TL	76	#define CONFIG_SPLASH_SCREEN
	77	#define CONFIG_LCD_LOGO
	78	#define CONFIG_SHARP_LQ035Q7DH06
	79	#endif
	80
	81	/* USB */
	82	#ifdef CONFIG_CMD_USB
a21d0c2c	83	#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
6d0f6bcf	84	#define CONFIG_SYS_USB_EHCI_CPU_INIT
1552af70 TL	85	#endif
	86
	87	/* Realtime clock */
	88	#define CONFIG_MCFRTC
	89	#undef RTC_DEBUG
6d0f6bcf	90	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
1552af70 TL	91
	92	/* Timer */
	93	#define CONFIG_MCFTMR
	94	#undef CONFIG_MCFPIT
	95
	96	/* I2c */
00f792e0 HS	97	#define CONFIG_SYS_I2C
	98	#define CONFIG_SYS_I2C_FSL
	99	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	100	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	101	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
a21d0c2c TL	102	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	103
	104	/* DSPI and Serial Flash */
	105	#define CONFIG_CF_DSPI
	106	#define CONFIG_HARD_SPI
a21d0c2c TL	107	#define CONFIG_SYS_SBFHDR_SIZE 0x7
	108	#ifdef CONFIG_CMD_SPI
	109	# define CONFIG_SYS_DSPI_CS2
a21d0c2c	110
ee0a8462 TL	111	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	112	DSPI_CTAR_PCSSCK_1CLK \| \
	113	DSPI_CTAR_PASC(0) \| \
	114	DSPI_CTAR_PDT(0) \| \
	115	DSPI_CTAR_CSSCK(0) \| \
	116	DSPI_CTAR_ASC(0) \| \
	117	DSPI_CTAR_DT(1))
a21d0c2c	118	#endif
1552af70 TL	119
	120	/* Input, PCI, Flexbus, and VCO */
	121	#define CONFIG_EXTRA_CLOCK
	122
6d0f6bcf	123	#define CONFIG_SYS_INPUT_CLKSRC 16000000
1552af70	124
a21d0c2c	125	#define CONFIG_PRAM 2048 /* 2048 KB */
1552af70	126
a21d0c2c	127	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
1552af70	128
6d0f6bcf	129	#define CONFIG_SYS_MBAR 0xFC000000
1552af70 TL	130
	131	/*
	132	* Low Level Configuration Settings
	133	* (address mappings, register initial values, etc.)
	134	* You should know what you are doing if you make changes here.
	135	*/
	136
a21d0c2c	137	/*
1552af70 TL	138	* Definitions for initial stack pointer and data area (in DPRAM)
1552af70 TL	139	*/
6d0f6bcf	140	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	141	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
a21d0c2c	142	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	143	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
a21d0c2c	144	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
553f0982	145	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
1552af70	146
a21d0c2c	147	/*
1552af70 TL	148	* Start addresses for the final memory configuration
1552af70 TL	149	* (Set up by the startup code)
6d0f6bcf	150	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
1552af70	151	*/
6d0f6bcf JCPV	152	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	153	#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
	154	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	155	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	156	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
	157	#define CONFIG_SYS_SDRAM_EMOD 0x81810000
	158	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
a21d0c2c	159	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
6d0f6bcf JCPV	160
	161	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	162	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	163
a21d0c2c	164	#ifdef CONFIG_CF_SBF
14d0a02a	165	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
a21d0c2c TL	166	#else
	167	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	168	#endif
6d0f6bcf JCPV	169	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	170	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	171	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
1552af70 TL	172
1552af70 TL	173	/* Initial Memory map for Linux */
6d0f6bcf	174	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	175	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
1552af70	176
a21d0c2c TL	177	/*
a21d0c2c TL	178	* Configuration for environment
27f7ae70 JJ	179	* Environment is not embedded in u-boot. First time runing may have env
27f7ae70 JJ	180	* crc error warning if there is no correct environment on the flash.
1552af70	181	*/
a21d0c2c	182	#ifdef CONFIG_CF_SBF
a21d0c2c	183	# define CONFIG_ENV_SPI_CS 2
a21d0c2c TL	184	#endif
a21d0c2c TL	185	#define CONFIG_ENV_OVERWRITE 1
1552af70 TL	186
	187	/*-----------------------------------------------------------------------
	188	* FLASH organization
	189	*/
a21d0c2c	190	#ifdef CONFIG_SYS_STMICRO_BOOT
ee0a8462	191	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
27f7ae70	192	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
a21d0c2c TL	193	# define CONFIG_ENV_OFFSET 0x30000
	194	# define CONFIG_ENV_SIZE 0x1000
	195	# define CONFIG_ENV_SECT_SIZE 0x10000
	196	#endif
	197	#ifdef CONFIG_SYS_SPANSION_BOOT
	198	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	199	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
27f7ae70	200	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
a21d0c2c TL	201	# define CONFIG_ENV_SIZE 0x1000
	202	# define CONFIG_ENV_SECT_SIZE 0x8000
	203	#endif
1552af70	204
6d0f6bcf JCPV	205	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	206	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	207	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff TL	208	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
bbf6bbff TL	209	# define CONFIG_FLASH_SPANSION_S29WS_N 1
6d0f6bcf JCPV	210	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	211	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	212	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	213	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	214	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	215	# define CONFIG_SYS_FLASH_CHECKSUM
a21d0c2c	216	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
1552af70 TL	217	#endif
1552af70 TL	218
5296cb1d	219	#define LDS_BOARD_TEXT \
	220	arch/m68k/cpu/mcf5227x/built-in.o (.text*) \
	221	arch/m68k/lib/built-in.o (.text*)
	222
1552af70 TL	223	/*
	224	* This is setting for JFFS2 support in u-boot.
	225	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	226	*/
	227	#ifdef CONFIG_CMD_JFFS2
	228	# define CONFIG_JFFS2_DEV "nor0"
	229	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
6d0f6bcf	230	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
1552af70 TL	231	#endif
	232
	233	/*-----------------------------------------------------------------------
	234	* Cache Configuration
	235	*/
a21d0c2c	236	#define CONFIG_SYS_CACHELINE_SIZE 16
1552af70	237
dd9f054e	238	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	239	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	240	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	241	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	242	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	243	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	244	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	245	CF_ACR_EN \| CF_ACR_SM_ALL)
	246	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	247	CF_CACR_DISD \| CF_CACR_INVI \| \
	248	CF_CACR_CEIB \| CF_CACR_DCM \| \
	249	CF_CACR_EUSP)
	250
1552af70 TL	251	/*-----------------------------------------------------------------------
	252	* Memory bank definitions
	253	*/
	254	/*
	255	* CS0 - NOR Flash
	256	* CS1 - Available
	257	* CS2 - Available
	258	* CS3 - Available
	259	* CS4 - Available
	260	* CS5 - Available
	261	*/
	262
a21d0c2c TL	263	#ifdef CONFIG_CF_SBF
	264	#define CONFIG_SYS_CS0_BASE 0x04000000
	265	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	266	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	267	#else
6d0f6bcf JCPV	268	#define CONFIG_SYS_CS0_BASE 0x00000000
	269	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	270	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
a21d0c2c	271	#endif
1552af70 TL	272
1552af70 TL	273	#endif /* _M52277EVB_H */