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1/*
2 * Configuation settings for the Freescale MCF5329 FireEngine board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
3765b3e7 7 * SPDX-License-Identifier: GPL-2.0+
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8 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5235EVB_H
15#define _M5235EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
4a442d31 21
4a442d31 22#define CONFIG_MCFUART
6d0f6bcf 23#define CONFIG_SYS_UART_PORT (0)
4a442d31 24#define CONFIG_BAUDRATE 115200
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25
26#undef CONFIG_WATCHDOG
27#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
28
29/*
30 * BOOTP options
31 */
32#define CONFIG_BOOTP_BOOTFILESIZE
33#define CONFIG_BOOTP_BOOTPATH
34#define CONFIG_BOOTP_GATEWAY
35#define CONFIG_BOOTP_HOSTNAME
36
37/* Command line configuration */
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38#define CONFIG_CMD_CACHE
39#define CONFIG_CMD_DHCP
40#define CONFIG_CMD_ELF
4a442d31 41#define CONFIG_CMD_I2C
4a442d31 42#define CONFIG_CMD_MII
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43#define CONFIG_CMD_PCI
44#define CONFIG_CMD_PING
45#define CONFIG_CMD_REGINFO
46
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47
48#define CONFIG_MCFFEC
49#ifdef CONFIG_MCFFEC
4a442d31 50# define CONFIG_MII 1
0f3ba7e9 51# define CONFIG_MII_INIT 1
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52# define CONFIG_SYS_DISCOVER_PHY
53# define CONFIG_SYS_RX_ETH_BUFFER 8
54# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
4a442d31 55
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56# define CONFIG_SYS_FEC0_PINMUX 0
57# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1 58# define MCFFEC_TOUT_LOOP 50000
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59/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
60# ifndef CONFIG_SYS_DISCOVER_PHY
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61# define FECDUPLEX FULL
62# define FECSPEED _100BASET
63# else
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64# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
65# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
4a442d31 66# endif
6d0f6bcf 67# endif /* CONFIG_SYS_DISCOVER_PHY */
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68#endif
69
70/* Timer */
71#define CONFIG_MCFTMR
72#undef CONFIG_MCFPIT
73
74/* I2C */
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75#define CONFIG_SYS_I2C
76#define CONFIG_SYS_i2C_FSL
77#define CONFIG_SYS_FSL_I2C_SPEED 80000
78#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
79#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
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80#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
81#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
82#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
83#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
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84
85/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
86#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
87#define CONFIG_BOOTFILE "u-boot.bin"
88#ifdef CONFIG_MCFFEC
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89# define CONFIG_IPADDR 192.162.1.2
90# define CONFIG_NETMASK 255.255.255.0
91# define CONFIG_SERVERIP 192.162.1.1
92# define CONFIG_GATEWAYIP 192.162.1.1
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93#endif /* FEC_ENET */
94
95#define CONFIG_HOSTNAME M5235EVB
96#define CONFIG_EXTRA_ENV_SETTINGS \
97 "netdev=eth0\0" \
98 "loadaddr=10000\0" \
99 "u-boot=u-boot.bin\0" \
100 "load=tftp ${loadaddr) ${u-boot}\0" \
101 "upd=run load; run prog\0" \
102 "prog=prot off ffe00000 ffe3ffff;" \
103 "era ffe00000 ffe3ffff;" \
104 "cp.b ${loadaddr} ffe00000 ${filesize};"\
105 "save\0" \
106 ""
107
108#define CONFIG_PRAM 512 /* 512 KB */
6d0f6bcf 109#define CONFIG_SYS_LONGHELP /* undef to save memory */
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110
111#if defined(CONFIG_KGDB)
6d0f6bcf 112# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
4a442d31 113#else
6d0f6bcf 114# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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115#endif
116
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117#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
118#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
119#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
120#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
4a442d31 121
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122#define CONFIG_SYS_CLK 75000000
123#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
4a442d31 124
6d0f6bcf 125#define CONFIG_SYS_MBAR 0x40000000
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126
127/*
128 * Low Level Configuration Settings
129 * (address mappings, register initial values, etc.)
130 * You should know what you are doing if you make changes here.
131 */
132/*-----------------------------------------------------------------------
133 * Definitions for initial stack pointer and data area (in DPRAM)
134 */
6d0f6bcf 135#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982 136#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
6d0f6bcf 137#define CONFIG_SYS_INIT_RAM_CTRL 0x21
25ddd1fb 138#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
6d0f6bcf 139#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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140
141/*-----------------------------------------------------------------------
142 * Start addresses for the final memory configuration
143 * (Set up by the startup code)
6d0f6bcf 144 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
4a442d31 145 */
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146#define CONFIG_SYS_SDRAM_BASE 0x00000000
147#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
4a442d31 148
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149#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
150#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
4a442d31 151
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152#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
153#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
4a442d31 154
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155#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
156#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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157
158/*
159 * For booting Linux, the board info and command line data
160 * have to be in the first 8 MB of memory, since this is
161 * the maximum mapped by the Linux kernel during initialization ??
162 */
163/* Initial Memory map for Linux */
6d0f6bcf 164#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4 165#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
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166
167/*-----------------------------------------------------------------------
168 * FLASH organization
169 */
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170#define CONFIG_SYS_FLASH_CFI
171#ifdef CONFIG_SYS_FLASH_CFI
00b1883a 172# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf 173# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
4a442d31 174#ifdef NORFLASH_PS32BIT
6d0f6bcf 175# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
4a442d31 176#else
6d0f6bcf 177# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
4a442d31 178#endif
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179# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
180# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
181# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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182#endif
183
012522fe 184#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
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185
186/* Configuration for environment
187 * Environment is embedded in u-boot in the second sector of the flash
188 */
5a1aceb0 189#define CONFIG_ENV_IS_IN_FLASH 1
5296cb1d 190
191#define LDS_BOARD_TEXT \
192 . = DEFINED(env_offset) ? env_offset : .; \
193 common/env_embedded.o (.text);
194
4a442d31 195#ifdef NORFLASH_PS32BIT
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196# define CONFIG_ENV_OFFSET (0x8000)
197# define CONFIG_ENV_SIZE 0x4000
198# define CONFIG_ENV_SECT_SIZE 0x4000
4a442d31 199#else
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200# define CONFIG_ENV_OFFSET (0x4000)
201# define CONFIG_ENV_SIZE 0x2000
202# define CONFIG_ENV_SECT_SIZE 0x2000
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203#endif
204
205/*-----------------------------------------------------------------------
206 * Cache Configuration
207 */
6d0f6bcf 208#define CONFIG_SYS_CACHELINE_SIZE 16
4a442d31 209
dd9f054e 210#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982 211 CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e 212#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982 213 CONFIG_SYS_INIT_RAM_SIZE - 4)
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214#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
215#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
216 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
217 CF_ACR_EN | CF_ACR_SM_ALL)
218#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
219 CF_CACR_CEIB | CF_CACR_DCM | \
220 CF_CACR_EUSP)
221
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222/*-----------------------------------------------------------------------
223 * Chipselect bank definitions
224 */
225/*
226 * CS0 - NOR Flash 1, 2, 4, or 8MB
227 * CS1 - Available
228 * CS2 - Available
229 * CS3 - Available
230 * CS4 - Available
231 * CS5 - Available
232 * CS6 - Available
233 * CS7 - Available
234 */
235#ifdef NORFLASH_PS32BIT
012522fe 236# define CONFIG_SYS_CS0_BASE 0xFFC00000
6d0f6bcf 237# define CONFIG_SYS_CS0_MASK 0x003f0001
012522fe 238# define CONFIG_SYS_CS0_CTRL 0x00001D00
4a442d31 239#else
012522fe 240# define CONFIG_SYS_CS0_BASE 0xFFE00000
6d0f6bcf 241# define CONFIG_SYS_CS0_MASK 0x001f0001
012522fe 242# define CONFIG_SYS_CS0_CTRL 0x00001D80
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243#endif
244
245#endif /* _M5329EVB_H */