[people/ms/u-boot.git] / include / configs / M5235EVB.h

/*
 * Configuation settings for the Freescale MCF5329 FireEngine board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5235EVB_H
#define _M5235EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF523x		/* define processor family */
#define CONFIG_M5235		/* define processor type */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO

#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hw support */
#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		80000
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x00000300
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(gpio->par_qspi)
#define CONFIG_SYS_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
#define CONFIG_BOOTFILE		"u-boot.bin"
#ifdef CONFIG_MCFFEC
#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M5235EVB
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */
#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_KGDB)
#	define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE+0x20000)

#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CLK			75000000
#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2

#define CONFIG_SYS_MBAR		0x40000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x21
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#ifdef NORFLASH_PS32BIT
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
#else
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#endif
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#ifdef NORFLASH_PS32BIT
#	define CONFIG_ENV_OFFSET		(0x8000)
#	define CONFIG_ENV_SIZE		0x4000
#	define CONFIG_ENV_SECT_SIZE	0x4000
#else
#	define CONFIG_ENV_OFFSET		(0x4000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x2000
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 * CS6 - Available
 * CS7 - Available
 */
#ifdef NORFLASH_PS32BIT
#	define CONFIG_SYS_CS0_BASE	0xFFC00000
#	define CONFIG_SYS_CS0_MASK	0x003f0001
#	define CONFIG_SYS_CS0_CTRL	0x00001D00
#else
#	define CONFIG_SYS_CS0_BASE	0xFFE00000
#	define CONFIG_SYS_CS0_MASK	0x001f0001
#	define CONFIG_SYS_CS0_CTRL	0x00001D80
#endif

#endif				/* _M5329EVB_H */
Commit	Line	Data
4a442d31 TL	1	/*
	2	* Configuation settings for the Freescale MCF5329 FireEngine board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
	30	#ifndef _M5235EVB_H
	31	#define _M5235EVB_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_MCF523x /* define processor family */
	38	#define CONFIG_M5235 /* define processor type */
	39
4a442d31	40	#define CONFIG_MCFUART
6d0f6bcf	41	#define CONFIG_SYS_UART_PORT (0)
4a442d31	42	#define CONFIG_BAUDRATE 115200
4a442d31 TL	43
	44	#undef CONFIG_WATCHDOG
	45	#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
	46
	47	/*
	48	* BOOTP options
	49	*/
	50	#define CONFIG_BOOTP_BOOTFILESIZE
	51	#define CONFIG_BOOTP_BOOTPATH
	52	#define CONFIG_BOOTP_GATEWAY
	53	#define CONFIG_BOOTP_HOSTNAME
	54
	55	/* Command line configuration */
	56	#include <config_cmd_default.h>
	57
	58	#define CONFIG_CMD_BOOTD
	59	#define CONFIG_CMD_CACHE
	60	#define CONFIG_CMD_DHCP
	61	#define CONFIG_CMD_ELF
	62	#define CONFIG_CMD_FLASH
	63	#define CONFIG_CMD_I2C
	64	#define CONFIG_CMD_MEMORY
	65	#define CONFIG_CMD_MISC
	66	#define CONFIG_CMD_MII
	67	#define CONFIG_CMD_NET
	68	#define CONFIG_CMD_PCI
	69	#define CONFIG_CMD_PING
	70	#define CONFIG_CMD_REGINFO
	71
	72	#undef CONFIG_CMD_LOADB
	73	#undef CONFIG_CMD_LOADS
	74
	75	#define CONFIG_MCFFEC
	76	#ifdef CONFIG_MCFFEC
4a442d31	77	# define CONFIG_MII 1
0f3ba7e9	78	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	79	# define CONFIG_SYS_DISCOVER_PHY
	80	# define CONFIG_SYS_RX_ETH_BUFFER 8
	81	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
4a442d31	82
6d0f6bcf JCPV	83	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	84	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	85	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	86	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	87	# ifndef CONFIG_SYS_DISCOVER_PHY
4a442d31 TL	88	# define FECDUPLEX FULL
	89	# define FECSPEED _100BASET
	90	# else
6d0f6bcf JCPV	91	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	92	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
4a442d31	93	# endif
6d0f6bcf	94	# endif /* CONFIG_SYS_DISCOVER_PHY */
4a442d31 TL	95	#endif
	96
	97	/* Timer */
	98	#define CONFIG_MCFTMR
	99	#undef CONFIG_MCFPIT
	100
	101	/* I2C */
	102	#define CONFIG_FSL_I2C
eec567a6 TL	103	#define CONFIG_HARD_I2C /* I2C with hw support */
eec567a6 TL	104	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	105	#define CONFIG_SYS_I2C_SPEED 80000
	106	#define CONFIG_SYS_I2C_SLAVE 0x7F
	107	#define CONFIG_SYS_I2C_OFFSET 0x00000300
	108	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	109	#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
	110	#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK \| GPIO_PAR_FECI2C_SDA_MASK)
	111	#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL \| GPIO_PAR_FECI2C_SDA_I2CSDA)
4a442d31 TL	112
	113	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	114	#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	115	#define CONFIG_BOOTFILE "u-boot.bin"
	116	#ifdef CONFIG_MCFFEC
	117	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	118	# define CONFIG_IPADDR 192.162.1.2
	119	# define CONFIG_NETMASK 255.255.255.0
	120	# define CONFIG_SERVERIP 192.162.1.1
	121	# define CONFIG_GATEWAYIP 192.162.1.1
	122	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	123	#endif /* FEC_ENET */
	124
	125	#define CONFIG_HOSTNAME M5235EVB
	126	#define CONFIG_EXTRA_ENV_SETTINGS \
	127	"netdev=eth0\0" \
	128	"loadaddr=10000\0" \
	129	"u-boot=u-boot.bin\0" \
	130	"load=tftp ${loadaddr) ${u-boot}\0" \
	131	"upd=run load; run prog\0" \
	132	"prog=prot off ffe00000 ffe3ffff;" \
	133	"era ffe00000 ffe3ffff;" \
	134	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	135	"save\0" \
	136	""
	137
	138	#define CONFIG_PRAM 512 /* 512 KB */
6d0f6bcf JCPV	139	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	140	#define CONFIG_SYS_LONGHELP /* undef to save memory */
4a442d31 TL	141
4a442d31 TL	142	#if defined(CONFIG_KGDB)
6d0f6bcf	143	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
4a442d31	144	#else
6d0f6bcf	145	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
4a442d31 TL	146	#endif
4a442d31 TL	147
6d0f6bcf JCPV	148	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	149	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	150	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	151	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
4a442d31	152
6d0f6bcf JCPV	153	#define CONFIG_SYS_HZ 1000
	154	#define CONFIG_SYS_CLK 75000000
	155	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
4a442d31	156
6d0f6bcf	157	#define CONFIG_SYS_MBAR 0x40000000
4a442d31 TL	158
	159	/*
	160	* Low Level Configuration Settings
	161	* (address mappings, register initial values, etc.)
	162	* You should know what you are doing if you make changes here.
	163	*/
	164	/*-----------------------------------------------------------------------
	165	* Definitions for initial stack pointer and data area (in DPRAM)
	166	*/
6d0f6bcf	167	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	168	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
6d0f6bcf	169	#define CONFIG_SYS_INIT_RAM_CTRL 0x21
25ddd1fb	170	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
6d0f6bcf	171	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
4a442d31 TL	172
	173	/*-----------------------------------------------------------------------
	174	* Start addresses for the final memory configuration
	175	* (Set up by the startup code)
6d0f6bcf	176	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
4a442d31	177	*/
6d0f6bcf JCPV	178	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	179	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
4a442d31	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
6d0f6bcf JCPV	182	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
4a442d31	183
6d0f6bcf JCPV	184	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d0f6bcf JCPV	185	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
4a442d31	186
6d0f6bcf JCPV	187	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	188	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
4a442d31 TL	189
	190	/*
	191	* For booting Linux, the board info and command line data
	192	* have to be in the first 8 MB of memory, since this is
	193	* the maximum mapped by the Linux kernel during initialization ??
	194	*/
	195	/* Initial Memory map for Linux */
6d0f6bcf	196	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	197	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
4a442d31 TL	198
	199	/*-----------------------------------------------------------------------
	200	* FLASH organization
	201	*/
6d0f6bcf JCPV	202	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	203	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	204	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf	205	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
4a442d31	206	#ifdef NORFLASH_PS32BIT
6d0f6bcf	207	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
4a442d31	208	#else
6d0f6bcf	209	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
4a442d31	210	#endif
6d0f6bcf JCPV	211	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	212	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	213	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
4a442d31 TL	214	#endif
4a442d31 TL	215
012522fe	216	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
4a442d31 TL	217
	218	/* Configuration for environment
	219	* Environment is embedded in u-boot in the second sector of the flash
	220	*/
5a1aceb0	221	#define CONFIG_ENV_IS_IN_FLASH 1
4a442d31	222	#ifdef NORFLASH_PS32BIT
0e8d1586 JCPV	223	# define CONFIG_ENV_OFFSET (0x8000)
	224	# define CONFIG_ENV_SIZE 0x4000
	225	# define CONFIG_ENV_SECT_SIZE 0x4000
4a442d31	226	#else
0e8d1586 JCPV	227	# define CONFIG_ENV_OFFSET (0x4000)
	228	# define CONFIG_ENV_SIZE 0x2000
	229	# define CONFIG_ENV_SECT_SIZE 0x2000
4a442d31 TL	230	#endif
	231
	232	/*-----------------------------------------------------------------------
	233	* Cache Configuration
	234	*/
6d0f6bcf	235	#define CONFIG_SYS_CACHELINE_SIZE 16
4a442d31	236
dd9f054e	237	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	238	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	239	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	240	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	241	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
	242	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	243	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	244	CF_ACR_EN \| CF_ACR_SM_ALL)
	245	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_DISD \| \
	246	CF_CACR_CEIB \| CF_CACR_DCM \| \
	247	CF_CACR_EUSP)
	248
4a442d31 TL	249	/*-----------------------------------------------------------------------
	250	* Chipselect bank definitions
	251	*/
	252	/*
	253	* CS0 - NOR Flash 1, 2, 4, or 8MB
	254	* CS1 - Available
	255	* CS2 - Available
	256	* CS3 - Available
	257	* CS4 - Available
	258	* CS5 - Available
	259	* CS6 - Available
	260	* CS7 - Available
	261	*/
	262	#ifdef NORFLASH_PS32BIT
012522fe	263	# define CONFIG_SYS_CS0_BASE 0xFFC00000
6d0f6bcf	264	# define CONFIG_SYS_CS0_MASK 0x003f0001
012522fe	265	# define CONFIG_SYS_CS0_CTRL 0x00001D00
4a442d31	266	#else
012522fe	267	# define CONFIG_SYS_CS0_BASE 0xFFE00000
6d0f6bcf	268	# define CONFIG_SYS_CS0_MASK 0x001f0001
012522fe	269	# define CONFIG_SYS_CS0_CTRL 0x00001D80
4a442d31 TL	270	#endif
	271
	272	#endif /* _M5329EVB_H */