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4a442d31 TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF5329 FireEngine board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
4a442d31 TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M5235EVB_H | |
15 | #define _M5235EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
4a442d31 | 21 | |
4a442d31 | 22 | #define CONFIG_MCFUART |
6d0f6bcf | 23 | #define CONFIG_SYS_UART_PORT (0) |
4a442d31 TL |
24 | |
25 | #undef CONFIG_WATCHDOG | |
26 | #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ | |
27 | ||
28 | /* | |
29 | * BOOTP options | |
30 | */ | |
31 | #define CONFIG_BOOTP_BOOTFILESIZE | |
32 | #define CONFIG_BOOTP_BOOTPATH | |
33 | #define CONFIG_BOOTP_GATEWAY | |
34 | #define CONFIG_BOOTP_HOSTNAME | |
35 | ||
4a442d31 TL |
36 | #define CONFIG_MCFFEC |
37 | #ifdef CONFIG_MCFFEC | |
4a442d31 | 38 | # define CONFIG_MII 1 |
0f3ba7e9 | 39 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
40 | # define CONFIG_SYS_DISCOVER_PHY |
41 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
42 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
4a442d31 | 43 | |
6d0f6bcf JCPV |
44 | # define CONFIG_SYS_FEC0_PINMUX 0 |
45 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 46 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
47 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
48 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
4a442d31 TL |
49 | # define FECDUPLEX FULL |
50 | # define FECSPEED _100BASET | |
51 | # else | |
6d0f6bcf JCPV |
52 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
53 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
4a442d31 | 54 | # endif |
6d0f6bcf | 55 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
4a442d31 TL |
56 | #endif |
57 | ||
58 | /* Timer */ | |
59 | #define CONFIG_MCFTMR | |
60 | #undef CONFIG_MCFPIT | |
61 | ||
62 | /* I2C */ | |
00f792e0 HS |
63 | #define CONFIG_SYS_I2C |
64 | #define CONFIG_SYS_i2C_FSL | |
65 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
66 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
67 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 | |
6d0f6bcf JCPV |
68 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
69 | #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) | |
70 | #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) | |
71 | #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) | |
4a442d31 TL |
72 | |
73 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
4a442d31 TL |
74 | #define CONFIG_BOOTFILE "u-boot.bin" |
75 | #ifdef CONFIG_MCFFEC | |
4a442d31 TL |
76 | # define CONFIG_IPADDR 192.162.1.2 |
77 | # define CONFIG_NETMASK 255.255.255.0 | |
78 | # define CONFIG_SERVERIP 192.162.1.1 | |
79 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
4a442d31 TL |
80 | #endif /* FEC_ENET */ |
81 | ||
82 | #define CONFIG_HOSTNAME M5235EVB | |
83 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
84 | "netdev=eth0\0" \ | |
85 | "loadaddr=10000\0" \ | |
86 | "u-boot=u-boot.bin\0" \ | |
87 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
88 | "upd=run load; run prog\0" \ | |
89 | "prog=prot off ffe00000 ffe3ffff;" \ | |
90 | "era ffe00000 ffe3ffff;" \ | |
91 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
92 | "save\0" \ | |
93 | "" | |
94 | ||
95 | #define CONFIG_PRAM 512 /* 512 KB */ | |
6d0f6bcf | 96 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
4a442d31 | 97 | |
6d0f6bcf | 98 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) |
4a442d31 | 99 | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_CLK 75000000 |
101 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 | |
4a442d31 | 102 | |
6d0f6bcf | 103 | #define CONFIG_SYS_MBAR 0x40000000 |
4a442d31 TL |
104 | |
105 | /* | |
106 | * Low Level Configuration Settings | |
107 | * (address mappings, register initial values, etc.) | |
108 | * You should know what you are doing if you make changes here. | |
109 | */ | |
110 | /*----------------------------------------------------------------------- | |
111 | * Definitions for initial stack pointer and data area (in DPRAM) | |
112 | */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 114 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 115 | #define CONFIG_SYS_INIT_RAM_CTRL 0x21 |
25ddd1fb | 116 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) |
6d0f6bcf | 117 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
4a442d31 TL |
118 | |
119 | /*----------------------------------------------------------------------- | |
120 | * Start addresses for the final memory configuration | |
121 | * (Set up by the startup code) | |
6d0f6bcf | 122 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
4a442d31 | 123 | */ |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
125 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
4a442d31 | 126 | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
128 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
4a442d31 | 129 | |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
131 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
4a442d31 | 132 | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
134 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
4a442d31 TL |
135 | |
136 | /* | |
137 | * For booting Linux, the board info and command line data | |
138 | * have to be in the first 8 MB of memory, since this is | |
139 | * the maximum mapped by the Linux kernel during initialization ?? | |
140 | */ | |
141 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 142 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 143 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
4a442d31 TL |
144 | |
145 | /*----------------------------------------------------------------------- | |
146 | * FLASH organization | |
147 | */ | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_FLASH_CFI |
149 | #ifdef CONFIG_SYS_FLASH_CFI | |
00b1883a | 150 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf | 151 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
4a442d31 | 152 | #ifdef NORFLASH_PS32BIT |
6d0f6bcf | 153 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
4a442d31 | 154 | #else |
6d0f6bcf | 155 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
4a442d31 | 156 | #endif |
6d0f6bcf JCPV |
157 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
158 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
159 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
4a442d31 TL |
160 | #endif |
161 | ||
012522fe | 162 | #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) |
4a442d31 TL |
163 | |
164 | /* Configuration for environment | |
165 | * Environment is embedded in u-boot in the second sector of the flash | |
166 | */ | |
5296cb1d | 167 | |
168 | #define LDS_BOARD_TEXT \ | |
169 | . = DEFINED(env_offset) ? env_offset : .; \ | |
0649cd0d | 170 | env/embedded.o(.text); |
5296cb1d | 171 | |
4a442d31 | 172 | #ifdef NORFLASH_PS32BIT |
0e8d1586 JCPV |
173 | # define CONFIG_ENV_OFFSET (0x8000) |
174 | # define CONFIG_ENV_SIZE 0x4000 | |
175 | # define CONFIG_ENV_SECT_SIZE 0x4000 | |
4a442d31 | 176 | #else |
0e8d1586 JCPV |
177 | # define CONFIG_ENV_OFFSET (0x4000) |
178 | # define CONFIG_ENV_SIZE 0x2000 | |
179 | # define CONFIG_ENV_SECT_SIZE 0x2000 | |
4a442d31 TL |
180 | #endif |
181 | ||
182 | /*----------------------------------------------------------------------- | |
183 | * Cache Configuration | |
184 | */ | |
6d0f6bcf | 185 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
4a442d31 | 186 | |
dd9f054e | 187 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 188 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 189 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 190 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
191 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) |
192 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
193 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
194 | CF_ACR_EN | CF_ACR_SM_ALL) | |
195 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ | |
196 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
197 | CF_CACR_EUSP) | |
198 | ||
4a442d31 TL |
199 | /*----------------------------------------------------------------------- |
200 | * Chipselect bank definitions | |
201 | */ | |
202 | /* | |
203 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
204 | * CS1 - Available | |
205 | * CS2 - Available | |
206 | * CS3 - Available | |
207 | * CS4 - Available | |
208 | * CS5 - Available | |
209 | * CS6 - Available | |
210 | * CS7 - Available | |
211 | */ | |
212 | #ifdef NORFLASH_PS32BIT | |
012522fe | 213 | # define CONFIG_SYS_CS0_BASE 0xFFC00000 |
6d0f6bcf | 214 | # define CONFIG_SYS_CS0_MASK 0x003f0001 |
012522fe | 215 | # define CONFIG_SYS_CS0_CTRL 0x00001D00 |
4a442d31 | 216 | #else |
012522fe | 217 | # define CONFIG_SYS_CS0_BASE 0xFFE00000 |
6d0f6bcf | 218 | # define CONFIG_SYS_CS0_MASK 0x001f0001 |
012522fe | 219 | # define CONFIG_SYS_CS0_CTRL 0x00001D80 |
4a442d31 TL |
220 | #endif |
221 | ||
222 | #endif /* _M5329EVB_H */ |