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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
4a442d31 TL |
2 | /* |
3 | * Configuation settings for the Freescale MCF5329 FireEngine board. | |
4 | * | |
5 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
4a442d31 TL |
7 | */ |
8 | ||
9 | /* | |
10 | * board/config.h - configuration options, board specific | |
11 | */ | |
12 | ||
13 | #ifndef _M5235EVB_H | |
14 | #define _M5235EVB_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | * (easy to change) | |
19 | */ | |
4a442d31 | 20 | |
4a442d31 | 21 | #define CONFIG_MCFUART |
6d0f6bcf | 22 | #define CONFIG_SYS_UART_PORT (0) |
4a442d31 TL |
23 | |
24 | #undef CONFIG_WATCHDOG | |
25 | #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ | |
26 | ||
27 | /* | |
28 | * BOOTP options | |
29 | */ | |
30 | #define CONFIG_BOOTP_BOOTFILESIZE | |
4a442d31 | 31 | |
4a442d31 | 32 | #ifdef CONFIG_MCFFEC |
0f3ba7e9 | 33 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
34 | # define CONFIG_SYS_DISCOVER_PHY |
35 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
36 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
6d0f6bcf JCPV |
37 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
38 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
4a442d31 TL |
39 | # define FECDUPLEX FULL |
40 | # define FECSPEED _100BASET | |
41 | # else | |
6d0f6bcf JCPV |
42 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
43 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
4a442d31 | 44 | # endif |
6d0f6bcf | 45 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
4a442d31 TL |
46 | #endif |
47 | ||
48 | /* Timer */ | |
49 | #define CONFIG_MCFTMR | |
4a442d31 TL |
50 | |
51 | /* I2C */ | |
00f792e0 HS |
52 | #define CONFIG_SYS_I2C |
53 | #define CONFIG_SYS_i2C_FSL | |
54 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
55 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
56 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 | |
6d0f6bcf JCPV |
57 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
58 | #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) | |
59 | #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) | |
60 | #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) | |
4a442d31 TL |
61 | |
62 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
4a442d31 TL |
63 | #define CONFIG_BOOTFILE "u-boot.bin" |
64 | #ifdef CONFIG_MCFFEC | |
4a442d31 TL |
65 | # define CONFIG_IPADDR 192.162.1.2 |
66 | # define CONFIG_NETMASK 255.255.255.0 | |
67 | # define CONFIG_SERVERIP 192.162.1.1 | |
68 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
4a442d31 TL |
69 | #endif /* FEC_ENET */ |
70 | ||
5bc0543d | 71 | #define CONFIG_HOSTNAME "M5235EVB" |
4a442d31 TL |
72 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
73 | "netdev=eth0\0" \ | |
74 | "loadaddr=10000\0" \ | |
75 | "u-boot=u-boot.bin\0" \ | |
76 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
77 | "upd=run load; run prog\0" \ | |
78 | "prog=prot off ffe00000 ffe3ffff;" \ | |
79 | "era ffe00000 ffe3ffff;" \ | |
80 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
81 | "save\0" \ | |
82 | "" | |
83 | ||
84 | #define CONFIG_PRAM 512 /* 512 KB */ | |
4a442d31 | 85 | |
6d0f6bcf | 86 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) |
4a442d31 | 87 | |
6d0f6bcf JCPV |
88 | #define CONFIG_SYS_CLK 75000000 |
89 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 | |
4a442d31 | 90 | |
6d0f6bcf | 91 | #define CONFIG_SYS_MBAR 0x40000000 |
4a442d31 TL |
92 | |
93 | /* | |
94 | * Low Level Configuration Settings | |
95 | * (address mappings, register initial values, etc.) | |
96 | * You should know what you are doing if you make changes here. | |
97 | */ | |
98 | /*----------------------------------------------------------------------- | |
99 | * Definitions for initial stack pointer and data area (in DPRAM) | |
100 | */ | |
6d0f6bcf | 101 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 102 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 103 | #define CONFIG_SYS_INIT_RAM_CTRL 0x21 |
25ddd1fb | 104 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) |
6d0f6bcf | 105 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
4a442d31 TL |
106 | |
107 | /*----------------------------------------------------------------------- | |
108 | * Start addresses for the final memory configuration | |
109 | * (Set up by the startup code) | |
6d0f6bcf | 110 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
4a442d31 | 111 | */ |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
113 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
4a442d31 | 114 | |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
116 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
4a442d31 | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
119 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
4a442d31 TL |
120 | |
121 | /* | |
122 | * For booting Linux, the board info and command line data | |
123 | * have to be in the first 8 MB of memory, since this is | |
124 | * the maximum mapped by the Linux kernel during initialization ?? | |
125 | */ | |
126 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 127 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 128 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
4a442d31 TL |
129 | |
130 | /*----------------------------------------------------------------------- | |
131 | * FLASH organization | |
132 | */ | |
6d0f6bcf | 133 | #ifdef CONFIG_SYS_FLASH_CFI |
6d0f6bcf | 134 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
4a442d31 | 135 | #ifdef NORFLASH_PS32BIT |
6d0f6bcf | 136 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
4a442d31 | 137 | #else |
6d0f6bcf | 138 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
4a442d31 | 139 | #endif |
6d0f6bcf JCPV |
140 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
141 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
4a442d31 TL |
142 | #endif |
143 | ||
012522fe | 144 | #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) |
4a442d31 TL |
145 | |
146 | /* Configuration for environment | |
147 | * Environment is embedded in u-boot in the second sector of the flash | |
148 | */ | |
5296cb1d | 149 | |
150 | #define LDS_BOARD_TEXT \ | |
151 | . = DEFINED(env_offset) ? env_offset : .; \ | |
0649cd0d | 152 | env/embedded.o(.text); |
5296cb1d | 153 | |
4a442d31 TL |
154 | /*----------------------------------------------------------------------- |
155 | * Cache Configuration | |
156 | */ | |
6d0f6bcf | 157 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
4a442d31 | 158 | |
dd9f054e | 159 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 160 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 161 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 162 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
163 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) |
164 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
165 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
166 | CF_ACR_EN | CF_ACR_SM_ALL) | |
167 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ | |
168 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
169 | CF_CACR_EUSP) | |
170 | ||
4a442d31 TL |
171 | /*----------------------------------------------------------------------- |
172 | * Chipselect bank definitions | |
173 | */ | |
174 | /* | |
175 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
176 | * CS1 - Available | |
177 | * CS2 - Available | |
178 | * CS3 - Available | |
179 | * CS4 - Available | |
180 | * CS5 - Available | |
181 | * CS6 - Available | |
182 | * CS7 - Available | |
183 | */ | |
184 | #ifdef NORFLASH_PS32BIT | |
012522fe | 185 | # define CONFIG_SYS_CS0_BASE 0xFFC00000 |
6d0f6bcf | 186 | # define CONFIG_SYS_CS0_MASK 0x003f0001 |
012522fe | 187 | # define CONFIG_SYS_CS0_CTRL 0x00001D00 |
4a442d31 | 188 | #else |
012522fe | 189 | # define CONFIG_SYS_CS0_BASE 0xFFE00000 |
6d0f6bcf | 190 | # define CONFIG_SYS_CS0_MASK 0x001f0001 |
012522fe | 191 | # define CONFIG_SYS_CS0_CTRL 0x00001D80 |
4a442d31 TL |
192 | #endif |
193 | ||
194 | #endif /* _M5329EVB_H */ |