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a605aacd TL |
1 | /* |
2 | * Configuation settings for the esd TASREG board. | |
3 | * | |
4 | * (C) Copyright 2004 | |
5 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
a605aacd TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M5249EVB_H | |
15 | #define _M5249EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
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21 | #define CONFIG_MCFTMR |
22 | ||
23 | #define CONFIG_MCFUART | |
6d0f6bcf | 24 | #define CONFIG_SYS_UART_PORT (0) |
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25 | |
26 | #undef CONFIG_WATCHDOG | |
27 | ||
28 | #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ | |
29 | ||
30 | /* | |
31 | * BOOTP options | |
32 | */ | |
33 | #undef CONFIG_BOOTP_BOOTFILESIZE | |
a605aacd TL |
34 | |
35 | /* | |
36 | * Command line configuration. | |
37 | */ | |
a605aacd | 38 | |
6d0f6bcf | 39 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
a605aacd TL |
40 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
41 | ||
6d0f6bcf | 42 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
a605aacd | 43 | |
6d0f6bcf JCPV |
44 | #define CONFIG_SYS_MEMTEST_START 0x400 |
45 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
a605aacd | 46 | |
a605aacd TL |
47 | /* |
48 | * Clock configuration: enable only one of the following options | |
49 | */ | |
50 | ||
6d0f6bcf JCPV |
51 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
52 | #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ | |
53 | #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ | |
a605aacd TL |
54 | |
55 | /* | |
56 | * Low Level Configuration Settings | |
57 | * (address mappings, register initial values, etc.) | |
58 | * You should know what you are doing if you make changes here. | |
59 | */ | |
60 | ||
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
62 | #define CONFIG_SYS_MBAR2 0x80000000 | |
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63 | |
64 | /*----------------------------------------------------------------------- | |
65 | * Definitions for initial stack pointer and data area (in DPRAM) | |
66 | */ | |
6d0f6bcf | 67 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 68 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
25ddd1fb | 69 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 70 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
a605aacd | 71 | |
5296cb1d | 72 | #define LDS_BOARD_TEXT \ |
0649cd0d SG |
73 | . = DEFINED(env_offset) ? env_offset : .; \ |
74 | env/embedded.o(.text); | |
5296cb1d | 75 | |
0e8d1586 JCPV |
76 | #define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ |
77 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
78 | #define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ | |
a605aacd TL |
79 | |
80 | /*----------------------------------------------------------------------- | |
81 | * Start addresses for the final memory configuration | |
82 | * (Set up by the startup code) | |
6d0f6bcf | 83 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a605aacd | 84 | */ |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
86 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
012522fe | 87 | #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) |
a605aacd TL |
88 | |
89 | #if 0 /* test-only */ | |
90 | #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ | |
91 | #endif | |
92 | ||
6d0f6bcf | 93 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
a605aacd | 94 | |
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
96 | #define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ | |
97 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
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98 | |
99 | /* | |
100 | * For booting Linux, the board info and command line data | |
101 | * have to be in the first 8 MB of memory, since this is | |
102 | * the maximum mapped by the Linux kernel during initialization ?? | |
103 | */ | |
6d0f6bcf | 104 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
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105 | |
106 | /*----------------------------------------------------------------------- | |
107 | * FLASH organization | |
108 | */ | |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_FLASH_CFI |
110 | #ifdef CONFIG_SYS_FLASH_CFI | |
a605aacd | 111 | |
00b1883a | 112 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
113 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
114 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
115 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
116 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
117 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
118 | # define CONFIG_SYS_FLASH_CHECKSUM | |
119 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
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120 | #endif |
121 | ||
122 | /*----------------------------------------------------------------------- | |
123 | * Cache Configuration | |
124 | */ | |
6d0f6bcf | 125 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
a605aacd | 126 | |
dd9f054e | 127 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 128 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 129 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 130 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
131 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) |
132 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ | |
133 | CF_ADDRMASK(2) | \ | |
134 | CF_ACR_EN | CF_ACR_SM_ALL) | |
135 | #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ | |
136 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
137 | CF_ACR_EN | CF_ACR_SM_ALL) | |
138 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ | |
139 | CF_CACR_DBWE) | |
140 | ||
a605aacd TL |
141 | /*----------------------------------------------------------------------- |
142 | * Memory bank definitions | |
143 | */ | |
144 | ||
145 | /* CS0 - AMD Flash, address 0xffc00000 */ | |
012522fe TL |
146 | #define CONFIG_SYS_CS0_BASE 0xffe00000 |
147 | #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ | |
a605aacd | 148 | /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ |
012522fe | 149 | #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ |
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150 | |
151 | /* CS1 - FPGA, address 0xe0000000 */ | |
012522fe TL |
152 | #define CONFIG_SYS_CS1_BASE 0xe0000000 |
153 | #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ | |
154 | #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ | |
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155 | |
156 | /*----------------------------------------------------------------------- | |
157 | * Port configuration | |
158 | */ | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
160 | #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ | |
161 | #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ | |
162 | #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ | |
163 | #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ | |
164 | #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ | |
165 | #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ | |
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166 | |
167 | #endif /* M5249 */ |