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6af3a0ea | 1 | /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
6d33c6ac TL |
2 | * Hayden Fraser (Hayden.Fraser@freescale.com) |
3 | * | |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
6d33c6ac TL |
5 | */ |
6 | ||
7 | #ifndef _M5253DEMO_H | |
8 | #define _M5253DEMO_H | |
9 | ||
6d33c6ac TL |
10 | #define CONFIG_M5253DEMO /* define board type */ |
11 | ||
12 | #define CONFIG_MCFTMR | |
13 | ||
14 | #define CONFIG_MCFUART | |
6d0f6bcf | 15 | #define CONFIG_SYS_UART_PORT (0) |
6d33c6ac | 16 | #define CONFIG_BAUDRATE 115200 |
6d33c6ac TL |
17 | |
18 | #undef CONFIG_WATCHDOG /* disable watchdog */ | |
19 | ||
6d33c6ac TL |
20 | |
21 | /* Configuration for environment | |
22 | * Environment is embedded in u-boot in the second sector of the flash | |
23 | */ | |
24 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
25 | # define CONFIG_ENV_OFFSET 0x4000 |
26 | # define CONFIG_ENV_SECT_SIZE 0x1000 | |
5a1aceb0 | 27 | # define CONFIG_ENV_IS_IN_FLASH 1 |
6d33c6ac | 28 | #else |
6d0f6bcf | 29 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) |
0e8d1586 | 30 | # define CONFIG_ENV_SECT_SIZE 0x1000 |
5a1aceb0 | 31 | # define CONFIG_ENV_IS_IN_FLASH 1 |
6d33c6ac TL |
32 | #endif |
33 | ||
5296cb1d | 34 | #define LDS_BOARD_TEXT \ |
35 | . = DEFINED(env_offset) ? env_offset : .; \ | |
36 | common/env_embedded.o (.text*); | |
37 | ||
6d33c6ac TL |
38 | /* |
39 | * Command line configuration. | |
40 | */ | |
6d33c6ac | 41 | #define CONFIG_CMD_IDE |
6d33c6ac TL |
42 | |
43 | #ifdef CONFIG_CMD_IDE | |
44 | /* ATA */ | |
45 | # define CONFIG_DOS_PARTITION | |
46 | # define CONFIG_MAC_PARTITION | |
47 | # define CONFIG_IDE_RESET 1 | |
48 | # define CONFIG_IDE_PREINIT 1 | |
49 | # define CONFIG_ATAPI | |
50 | # undef CONFIG_LBA48 | |
51 | ||
6d0f6bcf JCPV |
52 | # define CONFIG_SYS_IDE_MAXBUS 1 |
53 | # define CONFIG_SYS_IDE_MAXDEVICE 2 | |
6d33c6ac | 54 | |
6d0f6bcf JCPV |
55 | # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) |
56 | # define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
6d33c6ac | 57 | |
6d0f6bcf JCPV |
58 | # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
59 | # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
60 | # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
61 | # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
6d33c6ac TL |
62 | #endif |
63 | ||
64 | #define CONFIG_DRIVER_DM9000 | |
65 | #ifdef CONFIG_DRIVER_DM9000 | |
012522fe | 66 | # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) |
6d33c6ac TL |
67 | # define DM9000_IO CONFIG_DM9000_BASE |
68 | # define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
69 | # undef CONFIG_DM9000_DEBUG | |
f73e7d67 | 70 | # define CONFIG_DM9000_BYTE_SWAPPED |
6d33c6ac | 71 | |
6d33c6ac TL |
72 | # define CONFIG_OVERWRITE_ETHADDR_ONCE |
73 | ||
74 | # define CONFIG_EXTRA_ENV_SETTINGS \ | |
75 | "netdev=eth0\0" \ | |
5368c55d | 76 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
6d33c6ac TL |
77 | "loadaddr=10000\0" \ |
78 | "u-boot=u-boot.bin\0" \ | |
79 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
80 | "upd=run load; run prog\0" \ | |
ac265f7f TL |
81 | "prog=prot off 0xff800000 0xff82ffff;" \ |
82 | "era 0xff800000 0xff82ffff;" \ | |
f26a2473 | 83 | "cp.b ${loadaddr} 0xff800000 ${filesize};" \ |
6d33c6ac TL |
84 | "save\0" \ |
85 | "" | |
86 | #endif | |
87 | ||
88 | #define CONFIG_HOSTNAME M5253DEMO | |
89 | ||
eec567a6 | 90 | /* I2C */ |
00f792e0 HS |
91 | #define CONFIG_SYS_I2C |
92 | #define CONFIG_SYS_I2C_FSL | |
93 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
94 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
95 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
97 | #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) | |
98 | #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) | |
99 | #define CONFIG_SYS_I2C_PINMUX_SET (0) | |
eec567a6 | 100 | |
6d0f6bcf | 101 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d33c6ac TL |
102 | |
103 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 104 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
6d33c6ac | 105 | #else |
6d0f6bcf | 106 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
6d33c6ac | 107 | #endif |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
109 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
110 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
6d33c6ac | 111 | |
6d0f6bcf | 112 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
6d33c6ac | 113 | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_MEMTEST_START 0x400 |
115 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
6d33c6ac | 116 | |
6d0f6bcf JCPV |
117 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
118 | #define CONFIG_SYS_FAST_CLK | |
119 | #ifdef CONFIG_SYS_FAST_CLK | |
120 | # define CONFIG_SYS_PLLCR 0x1243E054 | |
121 | # define CONFIG_SYS_CLK 140000000 | |
6d33c6ac | 122 | #else |
6d0f6bcf JCPV |
123 | # define CONFIG_SYS_PLLCR 0x135a4140 |
124 | # define CONFIG_SYS_CLK 70000000 | |
6d33c6ac TL |
125 | #endif |
126 | ||
127 | /* | |
128 | * Low Level Configuration Settings | |
129 | * (address mappings, register initial values, etc.) | |
130 | * You should know what you are doing if you make changes here. | |
131 | */ | |
132 | ||
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
134 | #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ | |
6d33c6ac TL |
135 | |
136 | /* | |
137 | * Definitions for initial stack pointer and data area (in DPRAM) | |
138 | */ | |
6d0f6bcf | 139 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 140 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 141 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 142 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
6d33c6ac TL |
143 | |
144 | /* | |
145 | * Start addresses for the final memory configuration | |
146 | * (Set up by the startup code) | |
6d0f6bcf | 147 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
6d33c6ac | 148 | */ |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
150 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
6d33c6ac TL |
151 | |
152 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 153 | # define CONFIG_SYS_MONITOR_BASE 0x20000 |
6d33c6ac | 154 | #else |
6d0f6bcf | 155 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
6d33c6ac TL |
156 | #endif |
157 | ||
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_MONITOR_LEN 0x40000 |
159 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
160 | #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) | |
6d33c6ac TL |
161 | |
162 | /* | |
163 | * For booting Linux, the board info and command line data | |
164 | * have to be in the first 8 MB of memory, since this is | |
165 | * the maximum mapped by the Linux kernel during initialization ?? | |
166 | */ | |
6d0f6bcf | 167 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 168 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
6d33c6ac TL |
169 | |
170 | /* FLASH organization */ | |
012522fe | 171 | #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
173 | #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ | |
174 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
6d33c6ac TL |
175 | |
176 | #define FLASH_SST6401B 0x200 | |
177 | #define SST_ID_xF6401B 0x236D236D | |
178 | ||
6d0f6bcf JCPV |
179 | #undef CONFIG_SYS_FLASH_CFI |
180 | #ifdef CONFIG_SYS_FLASH_CFI | |
6d33c6ac TL |
181 | /* |
182 | * Unable to use CFI driver, due to incompatible sector erase command by SST. | |
183 | * Amd/Atmel use 0x30 for sector erase, SST use 0x50. | |
184 | * 0x30 is block erase in SST | |
185 | */ | |
0de0afbc | 186 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
187 | # define CONFIG_SYS_FLASH_SIZE 0x800000 |
188 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
6d33c6ac TL |
189 | # define CONFIG_FLASH_CFI_LEGACY |
190 | #else | |
6d0f6bcf JCPV |
191 | # define CONFIG_SYS_SST_SECT 2048 |
192 | # define CONFIG_SYS_SST_SECTSZ 0x1000 | |
193 | # define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
6d33c6ac TL |
194 | #endif |
195 | ||
196 | /* Cache Configuration */ | |
6d0f6bcf | 197 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
6d33c6ac | 198 | |
dd9f054e | 199 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 200 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 201 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 202 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
203 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) |
204 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ | |
205 | CF_ADDRMASK(8) | \ | |
206 | CF_ACR_EN | CF_ACR_SM_ALL) | |
207 | #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ | |
208 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
209 | CF_ACR_EN | CF_ACR_SM_ALL) | |
210 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ | |
211 | CF_CACR_DBWE) | |
212 | ||
6d33c6ac | 213 | /* Port configuration */ |
6d0f6bcf | 214 | #define CONFIG_SYS_FECI2C 0xF0 |
6d33c6ac | 215 | |
012522fe TL |
216 | #define CONFIG_SYS_CS0_BASE 0xFF800000 |
217 | #define CONFIG_SYS_CS0_MASK 0x007F0021 | |
218 | #define CONFIG_SYS_CS0_CTRL 0x00001D80 | |
6d33c6ac | 219 | |
012522fe TL |
220 | #define CONFIG_SYS_CS1_BASE 0xE0000000 |
221 | #define CONFIG_SYS_CS1_MASK 0x00000001 | |
222 | #define CONFIG_SYS_CS1_CTRL 0x00003DD8 | |
6d33c6ac TL |
223 | |
224 | /*----------------------------------------------------------------------- | |
225 | * Port configuration | |
226 | */ | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
228 | #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ | |
229 | #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ | |
230 | #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ | |
231 | #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ | |
232 | #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ | |
233 | #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ | |
6d33c6ac TL |
234 | |
235 | #endif /* _M5253DEMO_H */ |