]>
Commit | Line | Data |
---|---|---|
6af3a0ea | 1 | /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
6d33c6ac TL |
2 | * Hayden Fraser (Hayden.Fraser@freescale.com) |
3 | * | |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
6d33c6ac TL |
5 | */ |
6 | ||
7 | #ifndef _M5253DEMO_H | |
8 | #define _M5253DEMO_H | |
9 | ||
6d33c6ac TL |
10 | #define CONFIG_M5253DEMO /* define board type */ |
11 | ||
12 | #define CONFIG_MCFTMR | |
13 | ||
14 | #define CONFIG_MCFUART | |
6d0f6bcf | 15 | #define CONFIG_SYS_UART_PORT (0) |
6d33c6ac TL |
16 | |
17 | #undef CONFIG_WATCHDOG /* disable watchdog */ | |
18 | ||
6d33c6ac TL |
19 | |
20 | /* Configuration for environment | |
21 | * Environment is embedded in u-boot in the second sector of the flash | |
22 | */ | |
23 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
24 | # define CONFIG_ENV_OFFSET 0x4000 |
25 | # define CONFIG_ENV_SECT_SIZE 0x1000 | |
6d33c6ac | 26 | #else |
6d0f6bcf | 27 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) |
0e8d1586 | 28 | # define CONFIG_ENV_SECT_SIZE 0x1000 |
6d33c6ac TL |
29 | #endif |
30 | ||
5296cb1d | 31 | #define LDS_BOARD_TEXT \ |
0649cd0d SG |
32 | . = DEFINED(env_offset) ? env_offset : .; \ |
33 | env/embedded.o(.text*); | |
5296cb1d | 34 | |
6d33c6ac TL |
35 | /* |
36 | * Command line configuration. | |
37 | */ | |
6d33c6ac | 38 | |
fc843a02 | 39 | #ifdef CONFIG_IDE |
6d33c6ac | 40 | /* ATA */ |
6d33c6ac TL |
41 | # define CONFIG_IDE_RESET 1 |
42 | # define CONFIG_IDE_PREINIT 1 | |
43 | # define CONFIG_ATAPI | |
44 | # undef CONFIG_LBA48 | |
45 | ||
6d0f6bcf JCPV |
46 | # define CONFIG_SYS_IDE_MAXBUS 1 |
47 | # define CONFIG_SYS_IDE_MAXDEVICE 2 | |
6d33c6ac | 48 | |
6d0f6bcf JCPV |
49 | # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) |
50 | # define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
6d33c6ac | 51 | |
6d0f6bcf JCPV |
52 | # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
53 | # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
54 | # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
55 | # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
6d33c6ac TL |
56 | #endif |
57 | ||
58 | #define CONFIG_DRIVER_DM9000 | |
59 | #ifdef CONFIG_DRIVER_DM9000 | |
012522fe | 60 | # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) |
6d33c6ac TL |
61 | # define DM9000_IO CONFIG_DM9000_BASE |
62 | # define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
63 | # undef CONFIG_DM9000_DEBUG | |
f73e7d67 | 64 | # define CONFIG_DM9000_BYTE_SWAPPED |
6d33c6ac | 65 | |
6d33c6ac TL |
66 | # define CONFIG_OVERWRITE_ETHADDR_ONCE |
67 | ||
68 | # define CONFIG_EXTRA_ENV_SETTINGS \ | |
69 | "netdev=eth0\0" \ | |
5368c55d | 70 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
6d33c6ac TL |
71 | "loadaddr=10000\0" \ |
72 | "u-boot=u-boot.bin\0" \ | |
73 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
74 | "upd=run load; run prog\0" \ | |
ac265f7f TL |
75 | "prog=prot off 0xff800000 0xff82ffff;" \ |
76 | "era 0xff800000 0xff82ffff;" \ | |
f26a2473 | 77 | "cp.b ${loadaddr} 0xff800000 ${filesize};" \ |
6d33c6ac TL |
78 | "save\0" \ |
79 | "" | |
80 | #endif | |
81 | ||
82 | #define CONFIG_HOSTNAME M5253DEMO | |
83 | ||
eec567a6 | 84 | /* I2C */ |
00f792e0 HS |
85 | #define CONFIG_SYS_I2C |
86 | #define CONFIG_SYS_I2C_FSL | |
87 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
88 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
89 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 | |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
91 | #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) | |
92 | #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) | |
93 | #define CONFIG_SYS_I2C_PINMUX_SET (0) | |
eec567a6 | 94 | |
6d0f6bcf | 95 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d33c6ac | 96 | |
6d0f6bcf | 97 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
6d33c6ac | 98 | |
6d0f6bcf | 99 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
6d33c6ac | 100 | |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_MEMTEST_START 0x400 |
102 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
6d33c6ac | 103 | |
6d0f6bcf JCPV |
104 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
105 | #define CONFIG_SYS_FAST_CLK | |
106 | #ifdef CONFIG_SYS_FAST_CLK | |
107 | # define CONFIG_SYS_PLLCR 0x1243E054 | |
108 | # define CONFIG_SYS_CLK 140000000 | |
6d33c6ac | 109 | #else |
6d0f6bcf JCPV |
110 | # define CONFIG_SYS_PLLCR 0x135a4140 |
111 | # define CONFIG_SYS_CLK 70000000 | |
6d33c6ac TL |
112 | #endif |
113 | ||
114 | /* | |
115 | * Low Level Configuration Settings | |
116 | * (address mappings, register initial values, etc.) | |
117 | * You should know what you are doing if you make changes here. | |
118 | */ | |
119 | ||
6d0f6bcf JCPV |
120 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
121 | #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ | |
6d33c6ac TL |
122 | |
123 | /* | |
124 | * Definitions for initial stack pointer and data area (in DPRAM) | |
125 | */ | |
6d0f6bcf | 126 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 127 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 128 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 129 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
6d33c6ac TL |
130 | |
131 | /* | |
132 | * Start addresses for the final memory configuration | |
133 | * (Set up by the startup code) | |
6d0f6bcf | 134 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
6d33c6ac | 135 | */ |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
137 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
6d33c6ac TL |
138 | |
139 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 140 | # define CONFIG_SYS_MONITOR_BASE 0x20000 |
6d33c6ac | 141 | #else |
6d0f6bcf | 142 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
6d33c6ac TL |
143 | #endif |
144 | ||
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_MONITOR_LEN 0x40000 |
146 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
147 | #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) | |
6d33c6ac TL |
148 | |
149 | /* | |
150 | * For booting Linux, the board info and command line data | |
151 | * have to be in the first 8 MB of memory, since this is | |
152 | * the maximum mapped by the Linux kernel during initialization ?? | |
153 | */ | |
6d0f6bcf | 154 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 155 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
6d33c6ac TL |
156 | |
157 | /* FLASH organization */ | |
012522fe | 158 | #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
160 | #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ | |
161 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
6d33c6ac TL |
162 | |
163 | #define FLASH_SST6401B 0x200 | |
164 | #define SST_ID_xF6401B 0x236D236D | |
165 | ||
6d0f6bcf JCPV |
166 | #undef CONFIG_SYS_FLASH_CFI |
167 | #ifdef CONFIG_SYS_FLASH_CFI | |
6d33c6ac TL |
168 | /* |
169 | * Unable to use CFI driver, due to incompatible sector erase command by SST. | |
170 | * Amd/Atmel use 0x30 for sector erase, SST use 0x50. | |
171 | * 0x30 is block erase in SST | |
172 | */ | |
0de0afbc | 173 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
174 | # define CONFIG_SYS_FLASH_SIZE 0x800000 |
175 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
6d33c6ac TL |
176 | # define CONFIG_FLASH_CFI_LEGACY |
177 | #else | |
6d0f6bcf JCPV |
178 | # define CONFIG_SYS_SST_SECT 2048 |
179 | # define CONFIG_SYS_SST_SECTSZ 0x1000 | |
180 | # define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
6d33c6ac TL |
181 | #endif |
182 | ||
183 | /* Cache Configuration */ | |
6d0f6bcf | 184 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
6d33c6ac | 185 | |
dd9f054e | 186 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 187 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 188 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 189 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
190 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) |
191 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ | |
192 | CF_ADDRMASK(8) | \ | |
193 | CF_ACR_EN | CF_ACR_SM_ALL) | |
194 | #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ | |
195 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
196 | CF_ACR_EN | CF_ACR_SM_ALL) | |
197 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ | |
198 | CF_CACR_DBWE) | |
199 | ||
6d33c6ac | 200 | /* Port configuration */ |
6d0f6bcf | 201 | #define CONFIG_SYS_FECI2C 0xF0 |
6d33c6ac | 202 | |
012522fe TL |
203 | #define CONFIG_SYS_CS0_BASE 0xFF800000 |
204 | #define CONFIG_SYS_CS0_MASK 0x007F0021 | |
205 | #define CONFIG_SYS_CS0_CTRL 0x00001D80 | |
6d33c6ac | 206 | |
012522fe TL |
207 | #define CONFIG_SYS_CS1_BASE 0xE0000000 |
208 | #define CONFIG_SYS_CS1_MASK 0x00000001 | |
209 | #define CONFIG_SYS_CS1_CTRL 0x00003DD8 | |
6d33c6ac TL |
210 | |
211 | /*----------------------------------------------------------------------- | |
212 | * Port configuration | |
213 | */ | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
215 | #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ | |
216 | #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ | |
217 | #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ | |
218 | #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ | |
219 | #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ | |
220 | #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ | |
6d33c6ac TL |
221 | |
222 | #endif /* _M5253DEMO_H */ |