[people/ms/u-boot.git] / include / configs / M5253DEMO.h

/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * Hayden Fraser (Hayden.Fraser@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _M5253DEMO_H
#define _M5253DEMO_H

#define CONFIG_M5253DEMO	/* define board type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG		/* disable watchdog */


/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_ENV_OFFSET		0x4000
#	define CONFIG_ENV_SECT_SIZE	0x1000
#	define CONFIG_ENV_IS_IN_FLASH	1
#else
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
#	define CONFIG_ENV_SECT_SIZE	0x1000
#	define CONFIG_ENV_IS_IN_FLASH	1
#endif

#define LDS_BOARD_TEXT \
        . = DEFINED(env_offset) ? env_offset : .; \
        common/env_embedded.o (.text*);

/*
 * Command line configuration.
 */
#define CONFIG_CMD_IDE

#ifdef CONFIG_CMD_IDE
/* ATA */
#	define CONFIG_IDE_RESET		1
#	define CONFIG_IDE_PREINIT	1
#	define CONFIG_ATAPI
#	undef CONFIG_LBA48

#	define CONFIG_SYS_IDE_MAXBUS		1
#	define CONFIG_SYS_IDE_MAXDEVICE	2

#	define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
#	define CONFIG_SYS_ATA_IDE0_OFFSET	0

#	define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
#	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
#	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
#endif

#define CONFIG_DRIVER_DM9000
#ifdef CONFIG_DRIVER_DM9000
#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
#	define DM9000_IO		CONFIG_DM9000_BASE
#	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
#	undef CONFIG_DM9000_DEBUG
#	define CONFIG_DM9000_BYTE_SWAPPED

#	define CONFIG_OVERWRITE_ETHADDR_ONCE

#	define CONFIG_EXTRA_ENV_SETTINGS		\
		"netdev=eth0\0"				\
		"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
		"loadaddr=10000\0"			\
		"u-boot=u-boot.bin\0"			\
		"load=tftp ${loadaddr) ${u-boot}\0"	\
		"upd=run load; run prog\0"		\
		"prog=prot off 0xff800000 0xff82ffff;"	\
		"era 0xff800000 0xff82ffff;"		\
		"cp.b ${loadaddr} 0xff800000 ${filesize};"	\
		"save\0"				\
		""
#endif

#define CONFIG_HOSTNAME		M5253DEMO

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000280
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET	(0)

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#	define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
#	define CONFIG_SYS_PLLCR	0x1243E054
#	define CONFIG_SYS_CLK		140000000
#else
#	define CONFIG_SYS_PLLCR	0x135a4140
#	define CONFIG_SYS_CLK		70000000
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */

#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define FLASH_SST6401B		0x200
#define SST_ID_xF6401B		0x236D236D

#undef CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
/*
 * Unable to use CFI driver, due to incompatible sector erase command by SST.
 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 * 0x30 is block erase in SST
 */
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_FLASH_CFI_LEGACY
#else
#	define CONFIG_SYS_SST_SECT		2048
#	define CONFIG_SYS_SST_SECTSZ		0x1000
#	define CONFIG_SYS_FLASH_WRITE_TOUT	500
#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
					 CF_ADDRMASK(8) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/* Port configuration */
#define CONFIG_SYS_FECI2C		0xF0

#define CONFIG_SYS_CS0_BASE		0xFF800000
#define CONFIG_SYS_CS0_MASK		0x007F0021
#define CONFIG_SYS_CS0_CTRL		0x00001D80

#define CONFIG_SYS_CS1_BASE		0xE0000000
#define CONFIG_SYS_CS1_MASK		0x00000001
#define CONFIG_SYS_CS1_CTRL		0x00003DD8

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */

#endif				/* _M5253DEMO_H */
Commit	Line	Data
6af3a0ea	1	/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6d33c6ac TL	2	* Hayden Fraser (Hayden.Fraser@freescale.com)
6d33c6ac TL	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
6d33c6ac TL	5	*/
	6
	7	#ifndef _M5253DEMO_H
	8	#define _M5253DEMO_H
	9
6d33c6ac TL	10	#define CONFIG_M5253DEMO /* define board type */
	11
	12	#define CONFIG_MCFTMR
	13
	14	#define CONFIG_MCFUART
6d0f6bcf	15	#define CONFIG_SYS_UART_PORT (0)
6d33c6ac TL	16
	17	#undef CONFIG_WATCHDOG /* disable watchdog */
	18
6d33c6ac TL	19
	20	/* Configuration for environment
	21	* Environment is embedded in u-boot in the second sector of the flash
	22	*/
	23	#ifdef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	24	# define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	25	# define CONFIG_ENV_SECT_SIZE 0x1000
5a1aceb0	26	# define CONFIG_ENV_IS_IN_FLASH 1
6d33c6ac	27	#else
6d0f6bcf	28	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
0e8d1586	29	# define CONFIG_ENV_SECT_SIZE 0x1000
5a1aceb0	30	# define CONFIG_ENV_IS_IN_FLASH 1
6d33c6ac TL	31	#endif
6d33c6ac TL	32
5296cb1d	33	#define LDS_BOARD_TEXT \
	34	. = DEFINED(env_offset) ? env_offset : .; \
	35	common/env_embedded.o (.text*);
	36
6d33c6ac TL	37	/*
	38	* Command line configuration.
	39	*/
6d33c6ac	40	#define CONFIG_CMD_IDE
6d33c6ac TL	41
	42	#ifdef CONFIG_CMD_IDE
	43	/* ATA */
6d33c6ac TL	44	# define CONFIG_IDE_RESET 1
	45	# define CONFIG_IDE_PREINIT 1
	46	# define CONFIG_ATAPI
	47	# undef CONFIG_LBA48
	48
6d0f6bcf JCPV	49	# define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	50	# define CONFIG_SYS_IDE_MAXDEVICE 2
6d33c6ac	51
6d0f6bcf JCPV	52	# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
6d0f6bcf JCPV	53	# define CONFIG_SYS_ATA_IDE0_OFFSET 0
6d33c6ac	54
6d0f6bcf JCPV	55	# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	56	# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	57	# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	58	# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
6d33c6ac TL	59	#endif
	60
	61	#define CONFIG_DRIVER_DM9000
	62	#ifdef CONFIG_DRIVER_DM9000
012522fe	63	# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE \| 0x300)
6d33c6ac TL	64	# define DM9000_IO CONFIG_DM9000_BASE
	65	# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	66	# undef CONFIG_DM9000_DEBUG
f73e7d67	67	# define CONFIG_DM9000_BYTE_SWAPPED
6d33c6ac	68
6d33c6ac TL	69	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	70
	71	# define CONFIG_EXTRA_ENV_SETTINGS \
	72	"netdev=eth0\0" \
5368c55d	73	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
6d33c6ac TL	74	"loadaddr=10000\0" \
	75	"u-boot=u-boot.bin\0" \
	76	"load=tftp ${loadaddr) ${u-boot}\0" \
	77	"upd=run load; run prog\0" \
ac265f7f TL	78	"prog=prot off 0xff800000 0xff82ffff;" \
ac265f7f TL	79	"era 0xff800000 0xff82ffff;" \
f26a2473	80	"cp.b ${loadaddr} 0xff800000 ${filesize};" \
6d33c6ac TL	81	"save\0" \
	82	""
	83	#endif
	84
	85	#define CONFIG_HOSTNAME M5253DEMO
	86
eec567a6	87	/* I2C */
00f792e0 HS	88	#define CONFIG_SYS_I2C
	89	#define CONFIG_SYS_I2C_FSL
	90	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	91	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	92	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
6d0f6bcf JCPV	93	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	94	#define CONFIG_SYS_I2C_PINMUX_REG ((u32 ) (CONFIG_SYS_MBAR+0x19C))
	95	#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
	96	#define CONFIG_SYS_I2C_PINMUX_SET (0)
eec567a6	97
6d0f6bcf	98	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d33c6ac TL	99
6d33c6ac TL	100	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	101	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
6d33c6ac	102	#else
6d0f6bcf	103	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6d33c6ac	104	#endif
6d0f6bcf JCPV	105	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	106	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	107	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
6d33c6ac	108
6d0f6bcf	109	#define CONFIG_SYS_LOAD_ADDR 0x00100000
6d33c6ac	110
6d0f6bcf JCPV	111	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	112	#define CONFIG_SYS_MEMTEST_END 0x380000
6d33c6ac	113
6d0f6bcf JCPV	114	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	115	#define CONFIG_SYS_FAST_CLK
	116	#ifdef CONFIG_SYS_FAST_CLK
	117	# define CONFIG_SYS_PLLCR 0x1243E054
	118	# define CONFIG_SYS_CLK 140000000
6d33c6ac	119	#else
6d0f6bcf JCPV	120	# define CONFIG_SYS_PLLCR 0x135a4140
6d0f6bcf JCPV	121	# define CONFIG_SYS_CLK 70000000
6d33c6ac TL	122	#endif
	123
	124	/*
	125	* Low Level Configuration Settings
	126	* (address mappings, register initial values, etc.)
	127	* You should know what you are doing if you make changes here.
	128	*/
	129
6d0f6bcf JCPV	130	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	131	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
6d33c6ac TL	132
	133	/*
	134	* Definitions for initial stack pointer and data area (in DPRAM)
	135	*/
6d0f6bcf	136	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	137	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	138	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	139	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6d33c6ac TL	140
	141	/*
	142	* Start addresses for the final memory configuration
	143	* (Set up by the startup code)
6d0f6bcf	144	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
6d33c6ac	145	*/
6d0f6bcf JCPV	146	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	147	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
6d33c6ac TL	148
6d33c6ac TL	149	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	150	# define CONFIG_SYS_MONITOR_BASE 0x20000
6d33c6ac	151	#else
6d0f6bcf	152	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d33c6ac TL	153	#endif
6d33c6ac TL	154
6d0f6bcf JCPV	155	#define CONFIG_SYS_MONITOR_LEN 0x40000
	156	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	157	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
6d33c6ac TL	158
	159	/*
	160	* For booting Linux, the board info and command line data
	161	* have to be in the first 8 MB of memory, since this is
	162	* the maximum mapped by the Linux kernel during initialization ??
	163	*/
6d0f6bcf	164	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	165	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
6d33c6ac TL	166
6d33c6ac TL	167	/* FLASH organization */
012522fe	168	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
6d0f6bcf JCPV	169	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	170	#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
	171	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
6d33c6ac TL	172
	173	#define FLASH_SST6401B 0x200
	174	#define SST_ID_xF6401B 0x236D236D
	175
6d0f6bcf JCPV	176	#undef CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	177	#ifdef CONFIG_SYS_FLASH_CFI
6d33c6ac TL	178	/*
	179	* Unable to use CFI driver, due to incompatible sector erase command by SST.
	180	* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
	181	* 0x30 is block erase in SST
	182	*/
0de0afbc	183	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	184	# define CONFIG_SYS_FLASH_SIZE 0x800000
6d0f6bcf JCPV	185	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
6d33c6ac TL	186	# define CONFIG_FLASH_CFI_LEGACY
6d33c6ac TL	187	#else
6d0f6bcf JCPV	188	# define CONFIG_SYS_SST_SECT 2048
	189	# define CONFIG_SYS_SST_SECTSZ 0x1000
	190	# define CONFIG_SYS_FLASH_WRITE_TOUT 500
6d33c6ac TL	191	#endif
	192
	193	/* Cache Configuration */
6d0f6bcf	194	#define CONFIG_SYS_CACHELINE_SIZE 16
6d33c6ac	195
dd9f054e	196	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	197	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	198	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	199	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	200	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	201	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
	202	CF_ADDRMASK(8) \| \
	203	CF_ACR_EN \| CF_ACR_SM_ALL)
	204	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	205	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	206	CF_ACR_EN \| CF_ACR_SM_ALL)
	207	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	208	CF_CACR_DBWE)
	209
6d33c6ac	210	/* Port configuration */
6d0f6bcf	211	#define CONFIG_SYS_FECI2C 0xF0
6d33c6ac	212
012522fe TL	213	#define CONFIG_SYS_CS0_BASE 0xFF800000
	214	#define CONFIG_SYS_CS0_MASK 0x007F0021
	215	#define CONFIG_SYS_CS0_CTRL 0x00001D80
6d33c6ac	216
012522fe TL	217	#define CONFIG_SYS_CS1_BASE 0xE0000000
	218	#define CONFIG_SYS_CS1_MASK 0x00000001
	219	#define CONFIG_SYS_CS1_CTRL 0x00003DD8
6d33c6ac TL	220
	221	/*-----------------------------------------------------------------------
	222	* Port configuration
	223	*/
6d0f6bcf JCPV	224	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	225	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
	226	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	227	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	228	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	229	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	230	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
6d33c6ac TL	231
6d33c6ac TL	232	#endif /* _M5253DEMO_H */