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6d33c6ac TL |
1 | /* |
2 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
3 | * Hayden Fraser (Hayden.Fraser@freescale.com) | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef _M5253DEMO_H | |
25 | #define _M5253DEMO_H | |
26 | ||
27 | #define CONFIG_MCF52x2 /* define processor family */ | |
28 | #define CONFIG_M5253 /* define processor type */ | |
29 | #define CONFIG_M5253DEMO /* define board type */ | |
30 | ||
31 | #define CONFIG_MCFTMR | |
32 | ||
33 | #define CONFIG_MCFUART | |
6d0f6bcf | 34 | #define CONFIG_SYS_UART_PORT (0) |
6d33c6ac | 35 | #define CONFIG_BAUDRATE 115200 |
6d33c6ac TL |
36 | |
37 | #undef CONFIG_WATCHDOG /* disable watchdog */ | |
38 | ||
39 | #define CONFIG_BOOTDELAY 5 | |
40 | ||
41 | /* Configuration for environment | |
42 | * Environment is embedded in u-boot in the second sector of the flash | |
43 | */ | |
44 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
45 | # define CONFIG_ENV_OFFSET 0x4000 |
46 | # define CONFIG_ENV_SECT_SIZE 0x1000 | |
5a1aceb0 | 47 | # define CONFIG_ENV_IS_IN_FLASH 1 |
6d33c6ac | 48 | #else |
6d0f6bcf | 49 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) |
0e8d1586 | 50 | # define CONFIG_ENV_SECT_SIZE 0x1000 |
5a1aceb0 | 51 | # define CONFIG_ENV_IS_IN_FLASH 1 |
6d33c6ac TL |
52 | #endif |
53 | ||
54 | /* | |
55 | * Command line configuration. | |
56 | */ | |
57 | #include <config_cmd_default.h> | |
58 | ||
dd9f054e | 59 | #define CONFIG_CMD_CACHE |
6d33c6ac TL |
60 | #define CONFIG_CMD_LOADB |
61 | #define CONFIG_CMD_LOADS | |
62 | #define CONFIG_CMD_EXT2 | |
63 | #define CONFIG_CMD_FAT | |
64 | #define CONFIG_CMD_IDE | |
65 | #define CONFIG_CMD_MEMORY | |
66 | #define CONFIG_CMD_MISC | |
67 | #define CONFIG_CMD_PING | |
68 | ||
69 | #ifdef CONFIG_CMD_IDE | |
70 | /* ATA */ | |
71 | # define CONFIG_DOS_PARTITION | |
72 | # define CONFIG_MAC_PARTITION | |
73 | # define CONFIG_IDE_RESET 1 | |
74 | # define CONFIG_IDE_PREINIT 1 | |
75 | # define CONFIG_ATAPI | |
76 | # undef CONFIG_LBA48 | |
77 | ||
6d0f6bcf JCPV |
78 | # define CONFIG_SYS_IDE_MAXBUS 1 |
79 | # define CONFIG_SYS_IDE_MAXDEVICE 2 | |
6d33c6ac | 80 | |
6d0f6bcf JCPV |
81 | # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) |
82 | # define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
6d33c6ac | 83 | |
6d0f6bcf JCPV |
84 | # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
85 | # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
86 | # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
87 | # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
6d33c6ac TL |
88 | #endif |
89 | ||
90 | #define CONFIG_DRIVER_DM9000 | |
91 | #ifdef CONFIG_DRIVER_DM9000 | |
012522fe | 92 | # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) |
6d33c6ac TL |
93 | # define DM9000_IO CONFIG_DM9000_BASE |
94 | # define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
95 | # undef CONFIG_DM9000_DEBUG | |
f73e7d67 | 96 | # define CONFIG_DM9000_BYTE_SWAPPED |
6d33c6ac | 97 | |
6d33c6ac TL |
98 | # define CONFIG_OVERWRITE_ETHADDR_ONCE |
99 | ||
100 | # define CONFIG_EXTRA_ENV_SETTINGS \ | |
101 | "netdev=eth0\0" \ | |
5368c55d | 102 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
6d33c6ac TL |
103 | "loadaddr=10000\0" \ |
104 | "u-boot=u-boot.bin\0" \ | |
105 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
106 | "upd=run load; run prog\0" \ | |
ac265f7f TL |
107 | "prog=prot off 0xff800000 0xff82ffff;" \ |
108 | "era 0xff800000 0xff82ffff;" \ | |
f26a2473 | 109 | "cp.b ${loadaddr} 0xff800000 ${filesize};" \ |
6d33c6ac TL |
110 | "save\0" \ |
111 | "" | |
112 | #endif | |
113 | ||
114 | #define CONFIG_HOSTNAME M5253DEMO | |
115 | ||
eec567a6 | 116 | /* I2C */ |
00f792e0 HS |
117 | #define CONFIG_SYS_I2C |
118 | #define CONFIG_SYS_I2C_FSL | |
119 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
120 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
121 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
123 | #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) | |
124 | #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) | |
125 | #define CONFIG_SYS_I2C_PINMUX_SET (0) | |
eec567a6 | 126 | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_PROMPT "=> " |
128 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
6d33c6ac TL |
129 | |
130 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 131 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
6d33c6ac | 132 | #else |
6d0f6bcf | 133 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
6d33c6ac | 134 | #endif |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
136 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
137 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
6d33c6ac | 138 | |
6d0f6bcf | 139 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
6d33c6ac | 140 | |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_MEMTEST_START 0x400 |
142 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
6d33c6ac | 143 | |
6d0f6bcf | 144 | #define CONFIG_SYS_HZ 1000 |
6d33c6ac | 145 | |
6d0f6bcf JCPV |
146 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
147 | #define CONFIG_SYS_FAST_CLK | |
148 | #ifdef CONFIG_SYS_FAST_CLK | |
149 | # define CONFIG_SYS_PLLCR 0x1243E054 | |
150 | # define CONFIG_SYS_CLK 140000000 | |
6d33c6ac | 151 | #else |
6d0f6bcf JCPV |
152 | # define CONFIG_SYS_PLLCR 0x135a4140 |
153 | # define CONFIG_SYS_CLK 70000000 | |
6d33c6ac TL |
154 | #endif |
155 | ||
156 | /* | |
157 | * Low Level Configuration Settings | |
158 | * (address mappings, register initial values, etc.) | |
159 | * You should know what you are doing if you make changes here. | |
160 | */ | |
161 | ||
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
163 | #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ | |
6d33c6ac TL |
164 | |
165 | /* | |
166 | * Definitions for initial stack pointer and data area (in DPRAM) | |
167 | */ | |
6d0f6bcf | 168 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 169 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 170 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 171 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
6d33c6ac TL |
172 | |
173 | /* | |
174 | * Start addresses for the final memory configuration | |
175 | * (Set up by the startup code) | |
6d0f6bcf | 176 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
6d33c6ac | 177 | */ |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
179 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
6d33c6ac TL |
180 | |
181 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 182 | # define CONFIG_SYS_MONITOR_BASE 0x20000 |
6d33c6ac | 183 | #else |
6d0f6bcf | 184 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
6d33c6ac TL |
185 | #endif |
186 | ||
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_MONITOR_LEN 0x40000 |
188 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
189 | #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) | |
6d33c6ac TL |
190 | |
191 | /* | |
192 | * For booting Linux, the board info and command line data | |
193 | * have to be in the first 8 MB of memory, since this is | |
194 | * the maximum mapped by the Linux kernel during initialization ?? | |
195 | */ | |
6d0f6bcf | 196 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 197 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
6d33c6ac TL |
198 | |
199 | /* FLASH organization */ | |
012522fe | 200 | #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
202 | #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ | |
203 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
6d33c6ac TL |
204 | |
205 | #define FLASH_SST6401B 0x200 | |
206 | #define SST_ID_xF6401B 0x236D236D | |
207 | ||
6d0f6bcf JCPV |
208 | #undef CONFIG_SYS_FLASH_CFI |
209 | #ifdef CONFIG_SYS_FLASH_CFI | |
6d33c6ac TL |
210 | /* |
211 | * Unable to use CFI driver, due to incompatible sector erase command by SST. | |
212 | * Amd/Atmel use 0x30 for sector erase, SST use 0x50. | |
213 | * 0x30 is block erase in SST | |
214 | */ | |
0de0afbc | 215 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
216 | # define CONFIG_SYS_FLASH_SIZE 0x800000 |
217 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
6d33c6ac TL |
218 | # define CONFIG_FLASH_CFI_LEGACY |
219 | #else | |
6d0f6bcf JCPV |
220 | # define CONFIG_SYS_SST_SECT 2048 |
221 | # define CONFIG_SYS_SST_SECTSZ 0x1000 | |
222 | # define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
6d33c6ac TL |
223 | #endif |
224 | ||
225 | /* Cache Configuration */ | |
6d0f6bcf | 226 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
6d33c6ac | 227 | |
dd9f054e | 228 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 229 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 230 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 231 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
232 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) |
233 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ | |
234 | CF_ADDRMASK(8) | \ | |
235 | CF_ACR_EN | CF_ACR_SM_ALL) | |
236 | #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ | |
237 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
238 | CF_ACR_EN | CF_ACR_SM_ALL) | |
239 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ | |
240 | CF_CACR_DBWE) | |
241 | ||
6d33c6ac | 242 | /* Port configuration */ |
6d0f6bcf | 243 | #define CONFIG_SYS_FECI2C 0xF0 |
6d33c6ac | 244 | |
012522fe TL |
245 | #define CONFIG_SYS_CS0_BASE 0xFF800000 |
246 | #define CONFIG_SYS_CS0_MASK 0x007F0021 | |
247 | #define CONFIG_SYS_CS0_CTRL 0x00001D80 | |
6d33c6ac | 248 | |
012522fe TL |
249 | #define CONFIG_SYS_CS1_BASE 0xE0000000 |
250 | #define CONFIG_SYS_CS1_MASK 0x00000001 | |
251 | #define CONFIG_SYS_CS1_CTRL 0x00003DD8 | |
6d33c6ac TL |
252 | |
253 | /*----------------------------------------------------------------------- | |
254 | * Port configuration | |
255 | */ | |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
257 | #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ | |
258 | #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ | |
259 | #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ | |
260 | #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ | |
261 | #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ | |
262 | #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ | |
6d33c6ac TL |
263 | |
264 | #endif /* _M5253DEMO_H */ |