[people/ms/u-boot.git] / include / configs / M5253DEMO.h

/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * Hayden Fraser (Hayden.Fraser@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _M5253DEMO_H
#define _M5253DEMO_H

#define CONFIG_M5253DEMO	/* define board type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#undef CONFIG_WATCHDOG		/* disable watchdog */

#define CONFIG_BOOTDELAY	5

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_ENV_OFFSET		0x4000
#	define CONFIG_ENV_SECT_SIZE	0x1000
#	define CONFIG_ENV_IS_IN_FLASH	1
#else
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
#	define CONFIG_ENV_SECT_SIZE	0x1000
#	define CONFIG_ENV_IS_IN_FLASH	1
#endif

#define LDS_BOARD_TEXT \
        . = DEFINED(env_offset) ? env_offset : .; \
        common/env_embedded.o (.text*);

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_PING

#ifdef CONFIG_CMD_IDE
/* ATA */
#	define CONFIG_DOS_PARTITION
#	define CONFIG_MAC_PARTITION
#	define CONFIG_IDE_RESET		1
#	define CONFIG_IDE_PREINIT	1
#	define CONFIG_ATAPI
#	undef CONFIG_LBA48

#	define CONFIG_SYS_IDE_MAXBUS		1
#	define CONFIG_SYS_IDE_MAXDEVICE	2

#	define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
#	define CONFIG_SYS_ATA_IDE0_OFFSET	0

#	define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
#	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
#	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
#endif

#define CONFIG_DRIVER_DM9000
#ifdef CONFIG_DRIVER_DM9000
#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
#	define DM9000_IO		CONFIG_DM9000_BASE
#	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
#	undef CONFIG_DM9000_DEBUG
#	define CONFIG_DM9000_BYTE_SWAPPED

#	define CONFIG_OVERWRITE_ETHADDR_ONCE

#	define CONFIG_EXTRA_ENV_SETTINGS		\
		"netdev=eth0\0"				\
		"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
		"loadaddr=10000\0"			\
		"u-boot=u-boot.bin\0"			\
		"load=tftp ${loadaddr) ${u-boot}\0"	\
		"upd=run load; run prog\0"		\
		"prog=prot off 0xff800000 0xff82ffff;"	\
		"era 0xff800000 0xff82ffff;"		\
		"cp.b ${loadaddr} 0xff800000 ${filesize};"	\
		"save\0"				\
		""
#endif

#define CONFIG_HOSTNAME		M5253DEMO

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000280
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET	(0)

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#	define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
#	define CONFIG_SYS_PLLCR	0x1243E054
#	define CONFIG_SYS_CLK		140000000
#else
#	define CONFIG_SYS_PLLCR	0x135a4140
#	define CONFIG_SYS_CLK		70000000
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */

#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define FLASH_SST6401B		0x200
#define SST_ID_xF6401B		0x236D236D

#undef CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
/*
 * Unable to use CFI driver, due to incompatible sector erase command by SST.
 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 * 0x30 is block erase in SST
 */
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_FLASH_CFI_LEGACY
#else
#	define CONFIG_SYS_SST_SECT		2048
#	define CONFIG_SYS_SST_SECTSZ		0x1000
#	define CONFIG_SYS_FLASH_WRITE_TOUT	500
#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
					 CF_ADDRMASK(8) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/* Port configuration */
#define CONFIG_SYS_FECI2C		0xF0

#define CONFIG_SYS_CS0_BASE		0xFF800000
#define CONFIG_SYS_CS0_MASK		0x007F0021
#define CONFIG_SYS_CS0_CTRL		0x00001D80

#define CONFIG_SYS_CS1_BASE		0xE0000000
#define CONFIG_SYS_CS1_MASK		0x00000001
#define CONFIG_SYS_CS1_CTRL		0x00003DD8

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */

#endif				/* _M5253DEMO_H */
Commit	Line	Data
6af3a0ea	1	/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6d33c6ac TL	2	* Hayden Fraser (Hayden.Fraser@freescale.com)
6d33c6ac TL	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
6d33c6ac TL	5	*/
	6
	7	#ifndef _M5253DEMO_H
	8	#define _M5253DEMO_H
	9
6d33c6ac TL	10	#define CONFIG_M5253DEMO /* define board type */
	11
	12	#define CONFIG_MCFTMR
	13
	14	#define CONFIG_MCFUART
6d0f6bcf	15	#define CONFIG_SYS_UART_PORT (0)
6d33c6ac	16	#define CONFIG_BAUDRATE 115200
6d33c6ac TL	17
	18	#undef CONFIG_WATCHDOG /* disable watchdog */
	19
	20	#define CONFIG_BOOTDELAY 5
	21
	22	/* Configuration for environment
	23	* Environment is embedded in u-boot in the second sector of the flash
	24	*/
	25	#ifdef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	26	# define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	27	# define CONFIG_ENV_SECT_SIZE 0x1000
5a1aceb0	28	# define CONFIG_ENV_IS_IN_FLASH 1
6d33c6ac	29	#else
6d0f6bcf	30	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
0e8d1586	31	# define CONFIG_ENV_SECT_SIZE 0x1000
5a1aceb0	32	# define CONFIG_ENV_IS_IN_FLASH 1
6d33c6ac TL	33	#endif
6d33c6ac TL	34
5296cb1d	35	#define LDS_BOARD_TEXT \
	36	. = DEFINED(env_offset) ? env_offset : .; \
	37	common/env_embedded.o (.text*);
	38
6d33c6ac TL	39	/*
	40	* Command line configuration.
	41	*/
	42	#include <config_cmd_default.h>
	43
dd9f054e	44	#define CONFIG_CMD_CACHE
6d33c6ac TL	45	#define CONFIG_CMD_LOADB
	46	#define CONFIG_CMD_LOADS
	47	#define CONFIG_CMD_EXT2
	48	#define CONFIG_CMD_FAT
	49	#define CONFIG_CMD_IDE
	50	#define CONFIG_CMD_MEMORY
	51	#define CONFIG_CMD_MISC
	52	#define CONFIG_CMD_PING
	53
	54	#ifdef CONFIG_CMD_IDE
	55	/* ATA */
	56	# define CONFIG_DOS_PARTITION
	57	# define CONFIG_MAC_PARTITION
	58	# define CONFIG_IDE_RESET 1
	59	# define CONFIG_IDE_PREINIT 1
	60	# define CONFIG_ATAPI
	61	# undef CONFIG_LBA48
	62
6d0f6bcf JCPV	63	# define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	64	# define CONFIG_SYS_IDE_MAXDEVICE 2
6d33c6ac	65
6d0f6bcf JCPV	66	# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
6d0f6bcf JCPV	67	# define CONFIG_SYS_ATA_IDE0_OFFSET 0
6d33c6ac	68
6d0f6bcf JCPV	69	# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	70	# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	71	# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	72	# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
6d33c6ac TL	73	#endif
	74
	75	#define CONFIG_DRIVER_DM9000
	76	#ifdef CONFIG_DRIVER_DM9000
012522fe	77	# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE \| 0x300)
6d33c6ac TL	78	# define DM9000_IO CONFIG_DM9000_BASE
	79	# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	80	# undef CONFIG_DM9000_DEBUG
f73e7d67	81	# define CONFIG_DM9000_BYTE_SWAPPED
6d33c6ac	82
6d33c6ac TL	83	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	84
	85	# define CONFIG_EXTRA_ENV_SETTINGS \
	86	"netdev=eth0\0" \
5368c55d	87	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
6d33c6ac TL	88	"loadaddr=10000\0" \
	89	"u-boot=u-boot.bin\0" \
	90	"load=tftp ${loadaddr) ${u-boot}\0" \
	91	"upd=run load; run prog\0" \
ac265f7f TL	92	"prog=prot off 0xff800000 0xff82ffff;" \
ac265f7f TL	93	"era 0xff800000 0xff82ffff;" \
f26a2473	94	"cp.b ${loadaddr} 0xff800000 ${filesize};" \
6d33c6ac TL	95	"save\0" \
	96	""
	97	#endif
	98
	99	#define CONFIG_HOSTNAME M5253DEMO
	100
eec567a6	101	/* I2C */
00f792e0 HS	102	#define CONFIG_SYS_I2C
	103	#define CONFIG_SYS_I2C_FSL
	104	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	105	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	106	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
6d0f6bcf JCPV	107	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	108	#define CONFIG_SYS_I2C_PINMUX_REG ((u32 ) (CONFIG_SYS_MBAR+0x19C))
	109	#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
	110	#define CONFIG_SYS_I2C_PINMUX_SET (0)
eec567a6	111
6d0f6bcf	112	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d33c6ac TL	113
6d33c6ac TL	114	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	115	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
6d33c6ac	116	#else
6d0f6bcf	117	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6d33c6ac	118	#endif
6d0f6bcf JCPV	119	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	120	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	121	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
6d33c6ac	122
6d0f6bcf	123	#define CONFIG_SYS_LOAD_ADDR 0x00100000
6d33c6ac	124
6d0f6bcf JCPV	125	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	126	#define CONFIG_SYS_MEMTEST_END 0x380000
6d33c6ac	127
6d0f6bcf JCPV	128	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	129	#define CONFIG_SYS_FAST_CLK
	130	#ifdef CONFIG_SYS_FAST_CLK
	131	# define CONFIG_SYS_PLLCR 0x1243E054
	132	# define CONFIG_SYS_CLK 140000000
6d33c6ac	133	#else
6d0f6bcf JCPV	134	# define CONFIG_SYS_PLLCR 0x135a4140
6d0f6bcf JCPV	135	# define CONFIG_SYS_CLK 70000000
6d33c6ac TL	136	#endif
	137
	138	/*
	139	* Low Level Configuration Settings
	140	* (address mappings, register initial values, etc.)
	141	* You should know what you are doing if you make changes here.
	142	*/
	143
6d0f6bcf JCPV	144	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	145	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
6d33c6ac TL	146
	147	/*
	148	* Definitions for initial stack pointer and data area (in DPRAM)
	149	*/
6d0f6bcf	150	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	151	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	152	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	153	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6d33c6ac TL	154
	155	/*
	156	* Start addresses for the final memory configuration
	157	* (Set up by the startup code)
6d0f6bcf	158	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
6d33c6ac	159	*/
6d0f6bcf JCPV	160	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	161	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
6d33c6ac TL	162
6d33c6ac TL	163	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	164	# define CONFIG_SYS_MONITOR_BASE 0x20000
6d33c6ac	165	#else
6d0f6bcf	166	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d33c6ac TL	167	#endif
6d33c6ac TL	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_MONITOR_LEN 0x40000
	170	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	171	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
6d33c6ac TL	172
	173	/*
	174	* For booting Linux, the board info and command line data
	175	* have to be in the first 8 MB of memory, since this is
	176	* the maximum mapped by the Linux kernel during initialization ??
	177	*/
6d0f6bcf	178	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	179	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
6d33c6ac TL	180
6d33c6ac TL	181	/* FLASH organization */
012522fe	182	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
6d0f6bcf JCPV	183	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	184	#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
	185	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
6d33c6ac TL	186
	187	#define FLASH_SST6401B 0x200
	188	#define SST_ID_xF6401B 0x236D236D
	189
6d0f6bcf JCPV	190	#undef CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	191	#ifdef CONFIG_SYS_FLASH_CFI
6d33c6ac TL	192	/*
	193	* Unable to use CFI driver, due to incompatible sector erase command by SST.
	194	* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
	195	* 0x30 is block erase in SST
	196	*/
0de0afbc	197	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	198	# define CONFIG_SYS_FLASH_SIZE 0x800000
6d0f6bcf JCPV	199	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
6d33c6ac TL	200	# define CONFIG_FLASH_CFI_LEGACY
6d33c6ac TL	201	#else
6d0f6bcf JCPV	202	# define CONFIG_SYS_SST_SECT 2048
	203	# define CONFIG_SYS_SST_SECTSZ 0x1000
	204	# define CONFIG_SYS_FLASH_WRITE_TOUT 500
6d33c6ac TL	205	#endif
	206
	207	/* Cache Configuration */
6d0f6bcf	208	#define CONFIG_SYS_CACHELINE_SIZE 16
6d33c6ac	209
dd9f054e	210	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	211	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	212	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	213	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	214	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	215	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
	216	CF_ADDRMASK(8) \| \
	217	CF_ACR_EN \| CF_ACR_SM_ALL)
	218	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	219	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	220	CF_ACR_EN \| CF_ACR_SM_ALL)
	221	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	222	CF_CACR_DBWE)
	223
6d33c6ac	224	/* Port configuration */
6d0f6bcf	225	#define CONFIG_SYS_FECI2C 0xF0
6d33c6ac	226
012522fe TL	227	#define CONFIG_SYS_CS0_BASE 0xFF800000
	228	#define CONFIG_SYS_CS0_MASK 0x007F0021
	229	#define CONFIG_SYS_CS0_CTRL 0x00001D80
6d33c6ac	230
012522fe TL	231	#define CONFIG_SYS_CS1_BASE 0xE0000000
	232	#define CONFIG_SYS_CS1_MASK 0x00000001
	233	#define CONFIG_SYS_CS1_CTRL 0x00003DD8
6d33c6ac TL	234
	235	/*-----------------------------------------------------------------------
	236	* Port configuration
	237	*/
6d0f6bcf JCPV	238	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	239	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
	240	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	241	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	242	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	243	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	244	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
6d33c6ac TL	245
6d33c6ac TL	246	#endif /* _M5253DEMO_H */