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a1436a84 TL |
1 | /* |
2 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
3 | * Hayden Fraser (Hayden.Fraser@freescale.com) | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
a1436a84 TL |
6 | */ |
7 | ||
8 | #ifndef _M5253EVBE_H | |
9 | #define _M5253EVBE_H | |
10 | ||
a1436a84 TL |
11 | #define CONFIG_MCFTMR |
12 | ||
13 | #define CONFIG_MCFUART | |
6d0f6bcf | 14 | #define CONFIG_SYS_UART_PORT (0) |
a1436a84 TL |
15 | |
16 | #undef CONFIG_WATCHDOG /* disable watchdog */ | |
17 | ||
a1436a84 TL |
18 | |
19 | /* Configuration for environment | |
20 | * Environment is embedded in u-boot in the second sector of the flash | |
21 | */ | |
22 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
23 | #define CONFIG_ENV_OFFSET 0x4000 |
24 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
a1436a84 | 25 | #else |
0e8d1586 JCPV |
26 | #define CONFIG_ENV_ADDR 0xffe04000 |
27 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
a1436a84 TL |
28 | #endif |
29 | ||
5296cb1d | 30 | #define LDS_BOARD_TEXT \ |
31 | . = DEFINED(env_offset) ? env_offset : .; \ | |
0649cd0d | 32 | env/embedded.o(.text) |
5296cb1d | 33 | |
a1436a84 TL |
34 | /* |
35 | * BOOTP options | |
36 | */ | |
37 | #undef CONFIG_BOOTP_BOOTFILESIZE | |
38 | #undef CONFIG_BOOTP_BOOTPATH | |
39 | #undef CONFIG_BOOTP_GATEWAY | |
40 | #undef CONFIG_BOOTP_HOSTNAME | |
41 | ||
42 | /* | |
43 | * Command line configuration. | |
44 | */ | |
a1436a84 TL |
45 | |
46 | /* ATA */ | |
a1436a84 TL |
47 | #define CONFIG_IDE_RESET 1 |
48 | #define CONFIG_IDE_PREINIT 1 | |
49 | #define CONFIG_ATAPI | |
50 | #undef CONFIG_LBA48 | |
51 | ||
6d0f6bcf JCPV |
52 | #define CONFIG_SYS_IDE_MAXBUS 1 |
53 | #define CONFIG_SYS_IDE_MAXDEVICE 2 | |
a1436a84 | 54 | |
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) |
56 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
a1436a84 | 57 | |
6d0f6bcf JCPV |
58 | #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
59 | #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
60 | #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
61 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
a1436a84 | 62 | |
6d0f6bcf | 63 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
a1436a84 | 64 | |
6d0f6bcf | 65 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
a1436a84 | 66 | |
6d0f6bcf JCPV |
67 | #define CONFIG_SYS_MEMTEST_START 0x400 |
68 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
a1436a84 | 69 | |
6d0f6bcf JCPV |
70 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
71 | #define CONFIG_SYS_FAST_CLK | |
72 | #ifdef CONFIG_SYS_FAST_CLK | |
73 | # define CONFIG_SYS_PLLCR 0x1243E054 | |
74 | # define CONFIG_SYS_CLK 140000000 | |
a1436a84 | 75 | #else |
6d0f6bcf JCPV |
76 | # define CONFIG_SYS_PLLCR 0x135a4140 |
77 | # define CONFIG_SYS_CLK 70000000 | |
a1436a84 TL |
78 | #endif |
79 | ||
80 | /* | |
81 | * Low Level Configuration Settings | |
82 | * (address mappings, register initial values, etc.) | |
83 | * You should know what you are doing if you make changes here. | |
84 | */ | |
85 | ||
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
87 | #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ | |
a1436a84 TL |
88 | |
89 | /* | |
90 | * Definitions for initial stack pointer and data area (in DPRAM) | |
91 | */ | |
6d0f6bcf | 92 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 93 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 94 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 95 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
a1436a84 TL |
96 | |
97 | /* | |
98 | * Start addresses for the final memory configuration | |
99 | * (Set up by the startup code) | |
6d0f6bcf | 100 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a1436a84 | 101 | */ |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
103 | #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */ | |
a1436a84 TL |
104 | |
105 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 106 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
a1436a84 | 107 | #else |
6d0f6bcf | 108 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
a1436a84 TL |
109 | #endif |
110 | ||
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_MONITOR_LEN 0x40000 |
112 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
113 | #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) | |
a1436a84 TL |
114 | |
115 | /* | |
116 | * For booting Linux, the board info and command line data | |
117 | * have to be in the first 8 MB of memory, since this is | |
118 | * the maximum mapped by the Linux kernel during initialization ?? | |
119 | */ | |
6d0f6bcf | 120 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 121 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
a1436a84 TL |
122 | |
123 | /* FLASH organization */ | |
012522fe | 124 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
6d0f6bcf JCPV |
125 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
126 | #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ | |
127 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
a1436a84 | 128 | |
6d0f6bcf | 129 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 130 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
131 | #define CONFIG_SYS_FLASH_SIZE 0x200000 |
132 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
a1436a84 TL |
133 | |
134 | /* Cache Configuration */ | |
6d0f6bcf | 135 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
a1436a84 | 136 | |
dd9f054e | 137 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 138 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 139 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 140 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
141 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) |
142 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ | |
143 | CF_ADDRMASK(2) | \ | |
144 | CF_ACR_EN | CF_ACR_SM_ALL) | |
145 | #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ | |
146 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
147 | CF_ACR_EN | CF_ACR_SM_ALL) | |
148 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ | |
149 | CF_CACR_DBWE) | |
150 | ||
a1436a84 | 151 | /* Port configuration */ |
6d0f6bcf | 152 | #define CONFIG_SYS_FECI2C 0xF0 |
a1436a84 | 153 | |
012522fe TL |
154 | #define CONFIG_SYS_CS0_BASE 0xFFE00000 |
155 | #define CONFIG_SYS_CS0_MASK 0x001F0021 | |
156 | #define CONFIG_SYS_CS0_CTRL 0x00001D80 | |
a1436a84 TL |
157 | |
158 | /*----------------------------------------------------------------------- | |
159 | * Port configuration | |
160 | */ | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
162 | #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ | |
163 | #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ | |
164 | #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ | |
165 | #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ | |
166 | #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ | |
167 | #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ | |
a1436a84 TL |
168 | |
169 | #endif /* _M5253EVB_H */ |