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a1436a84 TL |
1 | /* |
2 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
3 | * Hayden Fraser (Hayden.Fraser@freescale.com) | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef _M5253EVBE_H | |
25 | #define _M5253EVBE_H | |
26 | ||
27 | #define CONFIG_MCF52x2 /* define processor family */ | |
28 | #define CONFIG_M5253 /* define processor type */ | |
29 | #define CONFIG_M5253EVBE /* define board type */ | |
30 | ||
31 | #define CONFIG_MCFTMR | |
32 | ||
33 | #define CONFIG_MCFUART | |
6d0f6bcf | 34 | #define CONFIG_SYS_UART_PORT (0) |
80ba61fd | 35 | #define CONFIG_BAUDRATE 115200 |
6d0f6bcf | 36 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
a1436a84 TL |
37 | |
38 | #undef CONFIG_WATCHDOG /* disable watchdog */ | |
39 | ||
40 | #define CONFIG_BOOTDELAY 5 | |
41 | ||
42 | /* Configuration for environment | |
43 | * Environment is embedded in u-boot in the second sector of the flash | |
44 | */ | |
45 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
46 | #define CONFIG_ENV_OFFSET 0x4000 |
47 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 48 | #define CONFIG_ENV_IS_IN_FLASH 1 |
a1436a84 | 49 | #else |
0e8d1586 JCPV |
50 | #define CONFIG_ENV_ADDR 0xffe04000 |
51 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 52 | #define CONFIG_ENV_IS_IN_FLASH 1 |
a1436a84 TL |
53 | #endif |
54 | ||
55 | /* | |
56 | * BOOTP options | |
57 | */ | |
58 | #undef CONFIG_BOOTP_BOOTFILESIZE | |
59 | #undef CONFIG_BOOTP_BOOTPATH | |
60 | #undef CONFIG_BOOTP_GATEWAY | |
61 | #undef CONFIG_BOOTP_HOSTNAME | |
62 | ||
63 | /* | |
64 | * Command line configuration. | |
65 | */ | |
66 | #include <config_cmd_default.h> | |
dd9f054e | 67 | #define CONFIG_CMD_CACHE |
a1436a84 TL |
68 | #undef CONFIG_CMD_NET |
69 | #define CONFIG_CMD_LOADB | |
70 | #define CONFIG_CMD_LOADS | |
71 | #define CONFIG_CMD_EXT2 | |
72 | #define CONFIG_CMD_FAT | |
73 | #define CONFIG_CMD_IDE | |
74 | #define CONFIG_CMD_MEMORY | |
75 | #define CONFIG_CMD_MISC | |
76 | ||
77 | /* ATA */ | |
78 | #define CONFIG_DOS_PARTITION | |
79 | #define CONFIG_MAC_PARTITION | |
80 | #define CONFIG_IDE_RESET 1 | |
81 | #define CONFIG_IDE_PREINIT 1 | |
82 | #define CONFIG_ATAPI | |
83 | #undef CONFIG_LBA48 | |
84 | ||
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_IDE_MAXBUS 1 |
86 | #define CONFIG_SYS_IDE_MAXDEVICE 2 | |
a1436a84 | 87 | |
6d0f6bcf JCPV |
88 | #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) |
89 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
a1436a84 | 90 | |
6d0f6bcf JCPV |
91 | #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
92 | #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
93 | #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
94 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
a1436a84 | 95 | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_PROMPT "=> " |
97 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
a1436a84 TL |
98 | |
99 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 100 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a1436a84 | 101 | #else |
6d0f6bcf | 102 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
a1436a84 | 103 | #endif |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
105 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
106 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a1436a84 | 107 | |
6d0f6bcf | 108 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
a1436a84 | 109 | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_MEMTEST_START 0x400 |
111 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
a1436a84 | 112 | |
6d0f6bcf | 113 | #define CONFIG_SYS_HZ 1000 |
a1436a84 | 114 | |
6d0f6bcf JCPV |
115 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
116 | #define CONFIG_SYS_FAST_CLK | |
117 | #ifdef CONFIG_SYS_FAST_CLK | |
118 | # define CONFIG_SYS_PLLCR 0x1243E054 | |
119 | # define CONFIG_SYS_CLK 140000000 | |
a1436a84 | 120 | #else |
6d0f6bcf JCPV |
121 | # define CONFIG_SYS_PLLCR 0x135a4140 |
122 | # define CONFIG_SYS_CLK 70000000 | |
a1436a84 TL |
123 | #endif |
124 | ||
125 | /* | |
126 | * Low Level Configuration Settings | |
127 | * (address mappings, register initial values, etc.) | |
128 | * You should know what you are doing if you make changes here. | |
129 | */ | |
130 | ||
6d0f6bcf JCPV |
131 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
132 | #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ | |
a1436a84 TL |
133 | |
134 | /* | |
135 | * Definitions for initial stack pointer and data area (in DPRAM) | |
136 | */ | |
6d0f6bcf | 137 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 138 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 139 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 140 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
a1436a84 TL |
141 | |
142 | /* | |
143 | * Start addresses for the final memory configuration | |
144 | * (Set up by the startup code) | |
6d0f6bcf | 145 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a1436a84 | 146 | */ |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
148 | #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */ | |
a1436a84 TL |
149 | |
150 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 151 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
a1436a84 | 152 | #else |
6d0f6bcf | 153 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
a1436a84 TL |
154 | #endif |
155 | ||
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_MONITOR_LEN 0x40000 |
157 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
158 | #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) | |
a1436a84 TL |
159 | |
160 | /* | |
161 | * For booting Linux, the board info and command line data | |
162 | * have to be in the first 8 MB of memory, since this is | |
163 | * the maximum mapped by the Linux kernel during initialization ?? | |
164 | */ | |
6d0f6bcf | 165 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 166 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
a1436a84 TL |
167 | |
168 | /* FLASH organization */ | |
012522fe | 169 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
171 | #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ | |
172 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
a1436a84 | 173 | |
6d0f6bcf | 174 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 175 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_FLASH_SIZE 0x200000 |
177 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
a1436a84 TL |
178 | |
179 | /* Cache Configuration */ | |
6d0f6bcf | 180 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
a1436a84 | 181 | |
dd9f054e | 182 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 183 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 184 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 185 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
186 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) |
187 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ | |
188 | CF_ADDRMASK(2) | \ | |
189 | CF_ACR_EN | CF_ACR_SM_ALL) | |
190 | #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ | |
191 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
192 | CF_ACR_EN | CF_ACR_SM_ALL) | |
193 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ | |
194 | CF_CACR_DBWE) | |
195 | ||
a1436a84 | 196 | /* Port configuration */ |
6d0f6bcf | 197 | #define CONFIG_SYS_FECI2C 0xF0 |
a1436a84 | 198 | |
012522fe TL |
199 | #define CONFIG_SYS_CS0_BASE 0xFFE00000 |
200 | #define CONFIG_SYS_CS0_MASK 0x001F0021 | |
201 | #define CONFIG_SYS_CS0_CTRL 0x00001D80 | |
a1436a84 TL |
202 | |
203 | /*----------------------------------------------------------------------- | |
204 | * Port configuration | |
205 | */ | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
207 | #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ | |
208 | #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ | |
209 | #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ | |
210 | #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ | |
211 | #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ | |
212 | #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ | |
a1436a84 TL |
213 | |
214 | #endif /* _M5253EVB_H */ |