[people/ms/u-boot.git] / include / configs / M5271EVB.h

/*
 * Configuation settings for the Freescale M5271EVB
 *
 * Based on MC5272C3 and r5200 board configs
 * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5271EVB_H
#define _M5271EVB_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_MCF52x2		/* define processor family */
#define CONFIG_M5271		/* define processor type */
#define CONFIG_M5271EVB		/* define board type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#undef CONFIG_WATCHDOG		/* disable watchdog */

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#else
#define CONFIG_ENV_ADDR		0xffe04000
#endif
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC

#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMDLINE_EDITING	1 /* enables command line history */
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds */
#define CONFIG_BOOTFILE		"u-boot.bin"
#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_RETRY_COUNT	5
#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M5271EVB
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"uboot=u-boot.bin\0"		\
	"load=tftp $loadaddr $uboot\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b $loadaddr ffe00000 $filesize;"	\
	"save\0"				\
	""

#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#define CONFIG_SYS_HZ			1000000

/* Clock configuration
 * The external oscillator is a 25.000 MHz
 * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
 * bus_clk = (cpu_clk/2) (fixed ratio)
 *
 * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
 * match the new clock speed. Max cpu_clk is 150 MHz.
 */
#define CONFIG_SYS_CLK			100000000
#define CONFIG_SYS_MCF_SYNCR 	(MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x40000000	/* Register Base Addrs */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		0xffe00000

#ifdef	CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/* FLASH organization */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks           */
#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip    */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_SIZE		0x200000

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/* Chip Select 0  : Boot Flash */
#define CONFIG_SYS_CS0_BASE	0xFFE00000
#define CONFIG_SYS_CS0_MASK	0x001F0001
#define CONFIG_SYS_CS0_CTRL	0x00001980

/* Chip Select 1 : External SRAM */
#define CONFIG_SYS_CS1_BASE	0x30000000
#define CONFIG_SYS_CS1_MASK	0x00070001
#define CONFIG_SYS_CS1_CTRL	0x00001900

#endif				/* _M5271EVB_H */
Commit	Line	Data
78b123cd MB	1	/*
	2	* Configuation settings for the Freescale M5271EVB
	3	*
	4	* Based on MC5272C3 and r5200 board configs
	5	* (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
	6	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/*
	28	* board/config.h - configuration options, board specific
	29	*/
	30
	31	#ifndef _M5271EVB_H
	32	#define _M5271EVB_H
	33
78b123cd MB	34	/*
	35	* High Level Configuration Options (easy to change)
	36	*/
	37	#define CONFIG_MCF52x2 /* define processor family */
	38	#define CONFIG_M5271 /* define processor type */
	39	#define CONFIG_M5271EVB /* define board type */
	40
f28e1bd9	41	#define CONFIG_MCFTMR
78b123cd	42
f28e1bd9	43	#define CONFIG_MCFUART
6d0f6bcf	44	#define CONFIG_SYS_UART_PORT (0)
79e0799c	45	#define CONFIG_BAUDRATE 115200
78b123cd MB	46
	47	#undef CONFIG_WATCHDOG /* disable watchdog */
	48
	49	/* Configuration for environment
	50	* Environment is embedded in u-boot in the second sector of the flash
	51	*/
	52	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586	53	#define CONFIG_ENV_OFFSET 0x4000
78b123cd	54	#else
0e8d1586	55	#define CONFIG_ENV_ADDR 0xffe04000
67c31036	56	#endif
0e8d1586	57	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	58	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	59	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
78b123cd	60
659e2f67 JL	61	/*
	62	* BOOTP options
	63	*/
	64	#define CONFIG_BOOTP_BOOTFILESIZE
	65	#define CONFIG_BOOTP_BOOTPATH
	66	#define CONFIG_BOOTP_GATEWAY
	67	#define CONFIG_BOOTP_HOSTNAME
	68
8353e139 JL	69	/*
	70	* Command line configuration.
	71	*/
	72	#include <config_cmd_default.h>
	73
dd9f054e	74	#define CONFIG_CMD_CACHE
8353e139 JL	75	#define CONFIG_CMD_PING
8353e139 JL	76	#define CONFIG_CMD_NET
f28e1bd9 TL	77	#define CONFIG_CMD_MII
	78	#define CONFIG_CMD_ELF
	79	#define CONFIG_CMD_FLASH
	80	#define CONFIG_CMD_I2C
	81	#define CONFIG_CMD_MEMORY
	82	#define CONFIG_CMD_MISC
8353e139 JL	83
8353e139 JL	84	#undef CONFIG_CMD_LOADS
8706ef37 RR	85	#define CONFIG_CMD_LOADB
	86	#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
	87	#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
78b123cd	88
f28e1bd9 TL	89	#define CONFIG_MCFFEC
f28e1bd9 TL	90	#ifdef CONFIG_MCFFEC
f28e1bd9	91	# define CONFIG_MII 1
0f3ba7e9	92	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	93	# define CONFIG_SYS_DISCOVER_PHY
	94	# define CONFIG_SYS_RX_ETH_BUFFER 8
	95	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	96
6d0f6bcf JCPV	97	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	98	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	99	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	100	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	101	# ifndef CONFIG_SYS_DISCOVER_PHY
f28e1bd9 TL	102	# define FECDUPLEX FULL
	103	# define FECSPEED _100BASET
	104	# else
6d0f6bcf JCPV	105	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	106	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	107	# endif
6d0f6bcf	108	# endif /* CONFIG_SYS_DISCOVER_PHY */
f28e1bd9 TL	109	#endif
	110
	111	/* I2C */
00f792e0 HS	112	#define CONFIG_SYS_I2C
	113	#define CONFIG_SYS_I2C_FSL
	114	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	115	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	116	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
6d0f6bcf	117	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
f28e1bd9	118
8706ef37	119	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
f28e1bd9 TL	120	#define CONFIG_BOOTFILE "u-boot.bin"
	121	#ifdef CONFIG_MCFFEC
	122	# define CONFIG_NET_RETRY_COUNT 5
	123	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	124	# define CONFIG_IPADDR 192.162.1.2
	125	# define CONFIG_NETMASK 255.255.255.0
	126	# define CONFIG_SERVERIP 192.162.1.1
	127	# define CONFIG_GATEWAYIP 192.162.1.1
	128	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	129	#endif /* FEC_ENET */
	130
8706ef37	131	#define CONFIG_HOSTNAME M5271EVB
f28e1bd9 TL	132	#define CONFIG_EXTRA_ENV_SETTINGS \
	133	"netdev=eth0\0" \
	134	"loadaddr=10000\0" \
8706ef37 RR	135	"uboot=u-boot.bin\0" \
8706ef37 RR	136	"load=tftp $loadaddr $uboot\0" \
f28e1bd9	137	"upd=run load; run prog\0" \
8706ef37 RR	138	"prog=prot off ffe00000 ffe3ffff;" \
	139	"era ffe00000 ffe3ffff;" \
	140	"cp.b $loadaddr ffe00000 $filesize;" \
f28e1bd9 TL	141	"save\0" \
f28e1bd9 TL	142	""
78b123cd	143
6d0f6bcf JCPV	144	#define CONFIG_SYS_PROMPT "=> "
6d0f6bcf JCPV	145	#define CONFIG_SYS_LONGHELP /* undef to save memory */
78b123cd	146
8353e139	147	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	148	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
78b123cd	149	#else
6d0f6bcf	150	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
78b123cd	151	#endif
6d0f6bcf JCPV	152	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	153	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	154	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
78b123cd	155
6d0f6bcf	156	#define CONFIG_SYS_LOAD_ADDR 0x00100000
78b123cd	157
6d0f6bcf JCPV	158	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	159	#define CONFIG_SYS_MEMTEST_END 0x380000
78b123cd	160
6d0f6bcf	161	#define CONFIG_SYS_HZ 1000000
8706ef37 RR	162
	163	/* Clock configuration
	164	* The external oscillator is a 25.000 MHz
	165	* CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
	166	* bus_clk = (cpu_clk/2) (fixed ratio)
	167	*
	168	* If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
	169	* match the new clock speed. Max cpu_clk is 150 MHz.
	170	*/
6d0f6bcf	171	#define CONFIG_SYS_CLK 100000000
8706ef37	172	#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X \| MCF_SYNCR_RFD_DIV1)
78b123cd MB	173
	174	/*
	175	* Low Level Configuration Settings
	176	* (address mappings, register initial values, etc.)
	177	* You should know what you are doing if you make changes here.
	178	*/
	179
6d0f6bcf	180	#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
78b123cd	181
78b123cd MB	182	/*
	183	* Definitions for initial stack pointer and data area (in DPRAM)
	184	*/
6d0f6bcf	185	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	186	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb	187	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	188	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
78b123cd MB	189
	190	/*
	191	* Start addresses for the final memory configuration
	192	* (Set up by the startup code)
6d0f6bcf	193	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
78b123cd	194	*/
6d0f6bcf JCPV	195	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	196	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
	197	#define CONFIG_SYS_FLASH_BASE 0xffe00000
78b123cd MB	198
78b123cd MB	199	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	200	#define CONFIG_SYS_MONITOR_BASE 0x20000
78b123cd	201	#else
6d0f6bcf	202	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
78b123cd MB	203	#endif
78b123cd MB	204
6d0f6bcf JCPV	205	#define CONFIG_SYS_MONITOR_LEN 0x40000
	206	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	207	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
78b123cd MB	208
	209	/*
	210	* For booting Linux, the board info and command line data
	211	* have to be in the first 8 MB of memory, since this is
	212	* the maximum mapped by the Linux kernel during initialization ??
	213	*/
6d0f6bcf	214	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
78b123cd MB	215
78b123cd MB	216	/* FLASH organization */
6d0f6bcf JCPV	217	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	218	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
	219	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
78b123cd	220
6d0f6bcf	221	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	222	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf	223	#define CONFIG_SYS_FLASH_SIZE 0x200000
78b123cd MB	224
78b123cd MB	225	/* Cache Configuration */
6d0f6bcf	226	#define CONFIG_SYS_CACHELINE_SIZE 16
78b123cd	227
dd9f054e	228	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	229	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	230	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	231	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	232	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	233	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	234	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	235	CF_ACR_EN \| CF_ACR_SM_ALL)
	236	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	237	CF_CACR_DISD \| CF_CACR_INVI \| \
	238	CF_CACR_CEIB \| CF_CACR_DCM \| \
	239	CF_CACR_EUSP)
	240
8706ef37 RR	241	/* Chip Select 0 : Boot Flash */
	242	#define CONFIG_SYS_CS0_BASE 0xFFE00000
	243	#define CONFIG_SYS_CS0_MASK 0x001F0001
	244	#define CONFIG_SYS_CS0_CTRL 0x00001980
	245
	246	/* Chip Select 1 : External SRAM */
	247	#define CONFIG_SYS_CS1_BASE 0x30000000
	248	#define CONFIG_SYS_CS1_MASK 0x00070001
	249	#define CONFIG_SYS_CS1_CTRL 0x00001900
78b123cd	250
f28e1bd9	251	#endif /* _M5271EVB_H */