[u-boot.git] / include / configs / M5272C3.h

/*
 * Configuation settings for the Motorola MC5272C3 board.
 *
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5272C3_H
#define _M5272C3_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF52x2		/* define processor family */
#define CONFIG_M5272		/* define processor type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */

#undef CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_MISC
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY

#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB

#define CONFIG_BOOTDELAY	5
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_MULTI		1
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#ifdef CONFIG_MCFFEC
#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* CONFIG_MCFFEC */

#define CONFIG_HOSTNAME		M5272C3
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
#endif

#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
#define CONFIG_SYS_LOAD_ADDR		0x20000
#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000
#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CLK			66000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_SCR			0x0003
#define CONFIG_SYS_SPR			0xffff

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		4	/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		0xffe00000

#ifdef	CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
#define CONFIG_SYS_OR0_PRELIM		0xFFE00014
#define CONFIG_SYS_BR1_PRELIM		0
#define CONFIG_SYS_OR1_PRELIM		0
#define CONFIG_SYS_BR2_PRELIM		0x30000001
#define CONFIG_SYS_OR2_PRELIM		0xFFF80000
#define CONFIG_SYS_BR3_PRELIM		0
#define CONFIG_SYS_OR3_PRELIM		0
#define CONFIG_SYS_BR4_PRELIM		0
#define CONFIG_SYS_OR4_PRELIM		0
#define CONFIG_SYS_BR5_PRELIM		0
#define CONFIG_SYS_OR5_PRELIM		0
#define CONFIG_SYS_BR6_PRELIM		0
#define CONFIG_SYS_OR6_PRELIM		0
#define CONFIG_SYS_BR7_PRELIM		0x00000701
#define CONFIG_SYS_OR7_PRELIM		0xFFC0007C

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_PACNT		0x00000000
#define CONFIG_SYS_PADDR		0x0000
#define CONFIG_SYS_PADAT		0x0000
#define CONFIG_SYS_PBCNT		0x55554155	/* Ethernet/UART configuration */
#define CONFIG_SYS_PBDDR		0x0000
#define CONFIG_SYS_PBDAT		0x0000
#define CONFIG_SYS_PDCNT		0x00000000
#endif				/* _M5272C3_H */
Commit	Line	Data
bf9e3b38 WD	1	/*
	2	* Configuation settings for the Motorola MC5272C3 board.
	3	*
	4	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
4e5ca3eb	24
bf9e3b38 WD	25	/*
	26	* board/config.h - configuration options, board specific
	27	*/
	28
	29	#ifndef _M5272C3_H
	30	#define _M5272C3_H
	31
	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
f28e1bd9 TL	36	#define CONFIG_MCF52x2 /* define processor family */
f28e1bd9 TL	37	#define CONFIG_M5272 /* define processor type */
4e5ca3eb	38
f28e1bd9	39	#define CONFIG_MCFTMR
4e5ca3eb	40
f28e1bd9	41	#define CONFIG_MCFUART
6d0f6bcf	42	#define CONFIG_SYS_UART_PORT (0)
79e0799c	43	#define CONFIG_BAUDRATE 115200
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
bf9e3b38	45
f28e1bd9	46	#undef CONFIG_WATCHDOG
bf9e3b38 WD	47	#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
bf9e3b38 WD	48
f28e1bd9	49	#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
bf9e3b38 WD	50
	51	/* Configuration for environment
	52	* Environment is embedded in u-boot in the second sector of the flash
	53	*/
	54	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	55	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	56	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	57	#define CONFIG_ENV_IS_IN_FLASH 1
bf9e3b38	58	#else
0e8d1586 JCPV	59	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	60	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	61	#define CONFIG_ENV_IS_IN_FLASH 1
bf9e3b38 WD	62	#endif
bf9e3b38 WD	63
659e2f67 JL	64	/*
	65	* BOOTP options
	66	*/
	67	#define CONFIG_BOOTP_BOOTFILESIZE
	68	#define CONFIG_BOOTP_BOOTPATH
	69	#define CONFIG_BOOTP_GATEWAY
	70	#define CONFIG_BOOTP_HOSTNAME
	71
8353e139 JL	72	/*
	73	* Command line configuration.
	74	*/
	75	#include <config_cmd_default.h>
	76
dd9f054e	77	#define CONFIG_CMD_CACHE
8353e139	78	#define CONFIG_CMD_MII
f28e1bd9 TL	79	#define CONFIG_CMD_NET
	80	#define CONFIG_CMD_PING
	81	#define CONFIG_CMD_MISC
	82	#define CONFIG_CMD_ELF
	83	#define CONFIG_CMD_FLASH
	84	#define CONFIG_CMD_MEMORY
8353e139 JL	85
	86	#undef CONFIG_CMD_LOADS
	87	#undef CONFIG_CMD_LOADB
	88
bf9e3b38	89	#define CONFIG_BOOTDELAY 5
f28e1bd9 TL	90	#define CONFIG_MCFFEC
	91	#ifdef CONFIG_MCFFEC
	92	# define CONFIG_NET_MULTI 1
	93	# define CONFIG_MII 1
d53cf6a9	94	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	95	# define CONFIG_SYS_DISCOVER_PHY
	96	# define CONFIG_SYS_RX_ETH_BUFFER 8
	97	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	98
6d0f6bcf JCPV	99	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	100	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	101	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	102	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	103	# ifndef CONFIG_SYS_DISCOVER_PHY
f28e1bd9 TL	104	# define FECDUPLEX FULL
	105	# define FECSPEED _100BASET
	106	# else
6d0f6bcf JCPV	107	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	108	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	109	# endif
6d0f6bcf	110	# endif /* CONFIG_SYS_DISCOVER_PHY */
f28e1bd9 TL	111	#endif
	112
	113	#ifdef CONFIG_MCFFEC
	114	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	115	# define CONFIG_IPADDR 192.162.1.2
	116	# define CONFIG_NETMASK 255.255.255.0
	117	# define CONFIG_SERVERIP 192.162.1.1
	118	# define CONFIG_GATEWAYIP 192.162.1.1
	119	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	120	#endif /* CONFIG_MCFFEC */
	121
	122	#define CONFIG_HOSTNAME M5272C3
	123	#define CONFIG_EXTRA_ENV_SETTINGS \
	124	"netdev=eth0\0" \
	125	"loadaddr=10000\0" \
	126	"u-boot=u-boot.bin\0" \
	127	"load=tftp ${loadaddr) ${u-boot}\0" \
	128	"upd=run load; run prog\0" \
	129	"prog=prot off ffe00000 ffe3ffff;" \
	130	"era ffe00000 ffe3ffff;" \
	131	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	132	"save\0" \
	133	""
bf9e3b38	134
6d0f6bcf JCPV	135	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	136	#define CONFIG_SYS_LONGHELP /* undef to save memory */
bf9e3b38	137
8353e139	138	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	139	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
bf9e3b38	140	#else
6d0f6bcf	141	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
bf9e3b38	142	#endif
bf9e3b38	143
6d0f6bcf JCPV	144	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	145	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	146	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	147	#define CONFIG_SYS_LOAD_ADDR 0x20000
	148	#define CONFIG_SYS_MEMTEST_START 0x400
	149	#define CONFIG_SYS_MEMTEST_END 0x380000
	150	#define CONFIG_SYS_HZ 1000
	151	#define CONFIG_SYS_CLK 66000000
bf9e3b38 WD	152
	153	/*
	154	* Low Level Configuration Settings
	155	* (address mappings, register initial values, etc.)
	156	* You should know what you are doing if you make changes here.
	157	*/
6d0f6bcf JCPV	158	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
	159	#define CONFIG_SYS_SCR 0x0003
	160	#define CONFIG_SYS_SPR 0xffff
bf9e3b38	161
bf9e3b38 WD	162	/*-----------------------------------------------------------------------
	163	* Definitions for initial stack pointer and data area (in DPRAM)
	164	*/
6d0f6bcf	165	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	166	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
6d0f6bcf	167	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
553f0982	168	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf	169	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
bf9e3b38 WD	170
	171	/*-----------------------------------------------------------------------
	172	* Start addresses for the final memory configuration
	173	* (Set up by the startup code)
6d0f6bcf	174	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
bf9e3b38	175	*/
6d0f6bcf JCPV	176	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	177	#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
	178	#define CONFIG_SYS_FLASH_BASE 0xffe00000
bf9e3b38 WD	179
bf9e3b38 WD	180	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	181	#define CONFIG_SYS_MONITOR_BASE 0x20000
bf9e3b38	182	#else
6d0f6bcf	183	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
bf9e3b38 WD	184	#endif
bf9e3b38 WD	185
6d0f6bcf JCPV	186	#define CONFIG_SYS_MONITOR_LEN 0x20000
	187	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	188	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
bf9e3b38 WD	189
	190	/*
	191	* For booting Linux, the board info and command line data
	192	* have to be in the first 8 MB of memory, since this is
	193	* the maximum mapped by the Linux kernel during initialization ??
	194	*/
6d0f6bcf	195	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
bf9e3b38	196
b202816c	197	/*
bf9e3b38 WD	198	* FLASH organization
bf9e3b38 WD	199	*/
b202816c TL	200	#define CONFIG_SYS_FLASH_CFI
	201	#ifdef CONFIG_SYS_FLASH_CFI
	202	# define CONFIG_FLASH_CFI_DRIVER 1
	203	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
	204	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	205	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	206	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	207	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	208	#endif
bf9e3b38 WD	209
	210	/*-----------------------------------------------------------------------
	211	* Cache Configuration
	212	*/
6d0f6bcf	213	#define CONFIG_SYS_CACHELINE_SIZE 16
bf9e3b38	214
dd9f054e	215	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	216	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	217	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	218	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	219	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	220	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	221	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	222	CF_ACR_EN \| CF_ACR_SM_ALL)
	223	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	224	CF_CACR_DISD \| CF_CACR_INVI \| \
	225	CF_CACR_CEIB \| CF_CACR_DCM \| \
	226	CF_CACR_EUSP)
	227
bf9e3b38 WD	228	/*-----------------------------------------------------------------------
	229	* Memory bank definitions
	230	*/
6d0f6bcf JCPV	231	#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
	232	#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
	233	#define CONFIG_SYS_BR1_PRELIM 0
	234	#define CONFIG_SYS_OR1_PRELIM 0
	235	#define CONFIG_SYS_BR2_PRELIM 0x30000001
	236	#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
	237	#define CONFIG_SYS_BR3_PRELIM 0
	238	#define CONFIG_SYS_OR3_PRELIM 0
	239	#define CONFIG_SYS_BR4_PRELIM 0
	240	#define CONFIG_SYS_OR4_PRELIM 0
	241	#define CONFIG_SYS_BR5_PRELIM 0
	242	#define CONFIG_SYS_OR5_PRELIM 0
	243	#define CONFIG_SYS_BR6_PRELIM 0
	244	#define CONFIG_SYS_OR6_PRELIM 0
	245	#define CONFIG_SYS_BR7_PRELIM 0x00000701
	246	#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
bf9e3b38 WD	247
	248	/*-----------------------------------------------------------------------
	249	* Port configuration
	250	*/
6d0f6bcf JCPV	251	#define CONFIG_SYS_PACNT 0x00000000
	252	#define CONFIG_SYS_PADDR 0x0000
	253	#define CONFIG_SYS_PADAT 0x0000
	254	#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
	255	#define CONFIG_SYS_PBDDR 0x0000
	256	#define CONFIG_SYS_PBDAT 0x0000
	257	#define CONFIG_SYS_PDCNT 0x00000000
f28e1bd9	258	#endif /* _M5272C3_H */