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bf9e3b38 WD |
1 | /* |
2 | * Configuation settings for the Motorola MC5272C3 board. | |
3 | * | |
4 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
4e5ca3eb | 24 | |
bf9e3b38 WD |
25 | /* |
26 | * board/config.h - configuration options, board specific | |
27 | */ | |
28 | ||
29 | #ifndef _M5272C3_H | |
30 | #define _M5272C3_H | |
31 | ||
32 | /* | |
33 | * High Level Configuration Options | |
34 | * (easy to change) | |
35 | */ | |
36 | #define CONFIG_MCF52x2 /* define processor family */ | |
37 | #define CONFIG_M5272 /* define processor type */ | |
4e5ca3eb WD |
38 | |
39 | #define FEC_ENET | |
40 | ||
bf9e3b38 WD |
41 | #define CONFIG_BAUDRATE 19200 |
42 | #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } | |
43 | ||
44 | #define CONFIG_WATCHDOG | |
45 | #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ | |
46 | ||
47 | #define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ | |
48 | ||
49 | /* Configuration for environment | |
50 | * Environment is embedded in u-boot in the second sector of the flash | |
51 | */ | |
52 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
53 | #define CFG_ENV_OFFSET 0x4000 | |
54 | #define CFG_ENV_SECT_SIZE 0x2000 | |
55 | #define CFG_ENV_IS_IN_FLASH 1 | |
56 | #define CFG_ENV_IS_EMBEDDED 1 | |
57 | #else | |
58 | #define CFG_ENV_ADDR 0xffe04000 | |
59 | #define CFG_ENV_SECT_SIZE 0x2000 | |
60 | #define CFG_ENV_IS_IN_FLASH 1 | |
61 | #endif | |
62 | ||
bf9e3b38 | 63 | |
659e2f67 JL |
64 | /* |
65 | * BOOTP options | |
66 | */ | |
67 | #define CONFIG_BOOTP_BOOTFILESIZE | |
68 | #define CONFIG_BOOTP_BOOTPATH | |
69 | #define CONFIG_BOOTP_GATEWAY | |
70 | #define CONFIG_BOOTP_HOSTNAME | |
71 | ||
72 | ||
8353e139 JL |
73 | /* |
74 | * Command line configuration. | |
75 | */ | |
76 | #include <config_cmd_default.h> | |
77 | ||
78 | #define CONFIG_CMD_MII | |
79 | ||
80 | #undef CONFIG_CMD_LOADS | |
81 | #undef CONFIG_CMD_LOADB | |
82 | ||
83 | ||
bf9e3b38 WD |
84 | #define CONFIG_BOOTDELAY 5 |
85 | ||
86 | #define CFG_PROMPT "-> " | |
87 | #define CFG_LONGHELP /* undef to save memory */ | |
88 | ||
8353e139 | 89 | #if defined(CONFIG_CMD_KGDB) |
bf9e3b38 WD |
90 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
91 | #else | |
92 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
93 | #endif | |
94 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
95 | #define CFG_MAXARGS 16 /* max number of command args */ | |
96 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
97 | ||
98 | #define CFG_LOAD_ADDR 0x20000 | |
99 | ||
100 | #define CFG_MEMTEST_START 0x400 | |
101 | #define CFG_MEMTEST_END 0x380000 | |
102 | ||
103 | #define CFG_HZ 1000 | |
104 | #define CFG_CLK 66000000 | |
105 | ||
106 | /* | |
107 | * Low Level Configuration Settings | |
108 | * (address mappings, register initial values, etc.) | |
109 | * You should know what you are doing if you make changes here. | |
110 | */ | |
111 | ||
112 | #define CFG_MBAR 0x10000000 /* Register Base Addrs */ | |
113 | ||
114 | #define CFG_SCR 0x0003; | |
115 | #define CFG_SPR 0xffff; | |
116 | ||
117 | #define CFG_DISCOVER_PHY | |
118 | #define CFG_ENET_BD_BASE 0x380000 | |
119 | ||
120 | /*----------------------------------------------------------------------- | |
121 | * Definitions for initial stack pointer and data area (in DPRAM) | |
122 | */ | |
123 | #define CFG_INIT_RAM_ADDR 0x20000000 | |
124 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ | |
125 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
126 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
127 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
128 | ||
129 | /*----------------------------------------------------------------------- | |
130 | * Start addresses for the final memory configuration | |
131 | * (Set up by the startup code) | |
132 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
133 | */ | |
134 | #define CFG_SDRAM_BASE 0x00000000 | |
135 | #define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ | |
136 | #define CFG_FLASH_BASE 0xffe00000 | |
137 | ||
138 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
139 | #define CFG_MONITOR_BASE 0x20000 | |
140 | #else | |
141 | #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) | |
142 | #endif | |
143 | ||
144 | #define CFG_MONITOR_LEN 0x20000 | |
145 | #define CFG_MALLOC_LEN (256 << 10) | |
146 | #define CFG_BOOTPARAMS_LEN 64*1024 | |
147 | ||
148 | /* | |
149 | * For booting Linux, the board info and command line data | |
150 | * have to be in the first 8 MB of memory, since this is | |
151 | * the maximum mapped by the Linux kernel during initialization ?? | |
152 | */ | |
153 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
154 | ||
155 | /*----------------------------------------------------------------------- | |
156 | * FLASH organization | |
157 | */ | |
158 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
159 | #define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ | |
160 | #define CFG_FLASH_ERASE_TOUT 1000 | |
161 | ||
162 | /*----------------------------------------------------------------------- | |
163 | * Cache Configuration | |
164 | */ | |
165 | #define CFG_CACHELINE_SIZE 16 | |
166 | ||
167 | /*----------------------------------------------------------------------- | |
168 | * Memory bank definitions | |
169 | */ | |
170 | #define CFG_BR0_PRELIM 0xFFE00201 | |
171 | #define CFG_OR0_PRELIM 0xFFE00014 | |
172 | ||
173 | #define CFG_BR1_PRELIM 0 | |
174 | #define CFG_OR1_PRELIM 0 | |
175 | ||
176 | #define CFG_BR2_PRELIM 0x30000001 | |
177 | #define CFG_OR2_PRELIM 0xFFF80000 | |
178 | ||
179 | #define CFG_BR3_PRELIM 0 | |
180 | #define CFG_OR3_PRELIM 0 | |
181 | ||
182 | #define CFG_BR4_PRELIM 0 | |
183 | #define CFG_OR4_PRELIM 0 | |
184 | ||
185 | #define CFG_BR5_PRELIM 0 | |
186 | #define CFG_OR5_PRELIM 0 | |
187 | ||
188 | #define CFG_BR6_PRELIM 0 | |
189 | #define CFG_OR6_PRELIM 0 | |
190 | ||
191 | #define CFG_BR7_PRELIM 0x00000701 | |
192 | #define CFG_OR7_PRELIM 0xFFC0007C | |
193 | ||
194 | /*----------------------------------------------------------------------- | |
195 | * Port configuration | |
196 | */ | |
197 | #define CFG_PACNT 0x00000000 | |
198 | #define CFG_PADDR 0x0000 | |
199 | #define CFG_PADAT 0x0000 | |
200 | #define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ | |
201 | #define CFG_PBDDR 0x0000 | |
202 | #define CFG_PBDAT 0x0000 | |
203 | #define CFG_PDCNT 0x00000000 | |
4e5ca3eb | 204 | |
bf9e3b38 | 205 | #endif /* _M5272C3_H */ |