[people/ms/u-boot.git] / include / configs / M5275EVB.h

/*
 * Configuation settings for the Motorola MC5275EVB board.
 *
 * By Arthur Shipkowski <art@videon-central.com>
 * Copyright (C) 2005 Videon Central, Inc.
 *
 * Based off of M5272C3 board code by Josef Baumgartner
 * <josef.baumgartner@telex.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5275EVB_H
#define _M5275EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_M5275EVB			/* define board type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#endif

#define LDS_BOARD_TEXT \
        . = DEFINED(env_offset) ? env_offset : .; \
        common/env_embedded.o (.text);

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Available command configuration */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DHCP


#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#define CONFIG_MII		1
#define CONFIG_MII_INIT		1
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_RX_ETH_BUFFER	8
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#define CONFIG_SYS_FEC0_PINMUX		0
#define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#define CONFIG_SYS_FEC1_PINMUX		0
#define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
#define MCFFEC_TOUT_LOOP	50000
#define CONFIG_HAS_ETH1
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#ifndef CONFIG_SYS_DISCOVER_PHY
#define FECDUPLEX		FULL
#define FECSPEED		_100BASET
#else
#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#endif
#endif
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(gpio_reg->par_feci2c)
#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET	(0x000F)

#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/

#if (CONFIG_CMD_KGDB)
#	define CONFIG_SYS_CBSIZE	1024
#else
#	define CONFIG_SYS_CBSIZE	256
#endif
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_LOAD_ADDR		0x800000

#define CONFIG_BOOTDELAY	5
#define CONFIG_BOOTCOMMAND	"bootm ffe40000"
#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_RETRY_COUNT	5
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* FEC_ENET */

#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${uboot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_SYS_CLK			150000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x40000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_SIZE		0x200000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
#define CONFIG_SYS_CS0_BASE		0xffe00000
#define CONFIG_SYS_CS0_CTRL		0x00001980
#define CONFIG_SYS_CS0_MASK		0x001F0001

#define CONFIG_SYS_CS1_BASE		0x30000000
#define CONFIG_SYS_CS1_CTRL		0x00001900
#define CONFIG_SYS_CS1_MASK		0x00070001

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_FECI2C		0x0FA0

#endif	/* _M5275EVB_H */
Commit	Line	Data
545c8e0a MF	1	/*
	2	* Configuation settings for the Motorola MC5275EVB board.
	3	*
	4	* By Arthur Shipkowski <art@videon-central.com>
	5	* Copyright (C) 2005 Videon Central, Inc.
	6	*
	7	* Based off of M5272C3 board code by Josef Baumgartner
	8	* <josef.baumgartner@telex.de>
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
545c8e0a MF	11	*/
	12
	13	/*
	14	* board/config.h - configuration options, board specific
	15	*/
	16
	17	#ifndef _M5275EVB_H
	18	#define _M5275EVB_H
	19
	20	/*
	21	* High Level Configuration Options
	22	* (easy to change)
	23	*/
545c8e0a MF	24	#define CONFIG_M5275EVB /* define board type */
	25
	26	#define CONFIG_MCFTMR
	27
	28	#define CONFIG_MCFUART
6d0f6bcf	29	#define CONFIG_SYS_UART_PORT (0)
79e0799c	30	#define CONFIG_BAUDRATE 115200
545c8e0a MF	31
	32	/* Configuration for environment
	33	* Environment is embedded in u-boot in the second sector of the flash
	34	*/
	35	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	36	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	37	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	38	#define CONFIG_ENV_IS_IN_FLASH 1
545c8e0a	39	#else
0e8d1586 JCPV	40	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	41	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	42	#define CONFIG_ENV_IS_IN_FLASH 1
545c8e0a MF	43	#endif
545c8e0a MF	44
5296cb1d	45	#define LDS_BOARD_TEXT \
	46	. = DEFINED(env_offset) ? env_offset : .; \
	47	common/env_embedded.o (.text);
	48
545c8e0a MF	49	/*
	50	* BOOTP options
	51	*/
	52	#define CONFIG_BOOTP_BOOTFILESIZE
	53	#define CONFIG_BOOTP_BOOTPATH
	54	#define CONFIG_BOOTP_GATEWAY
	55	#define CONFIG_BOOTP_HOSTNAME
	56
	57	/* Available command configuration */
dd9f054e	58	#define CONFIG_CMD_CACHE
545c8e0a MF	59	#define CONFIG_CMD_PING
545c8e0a MF	60	#define CONFIG_CMD_MII
545c8e0a	61	#define CONFIG_CMD_I2C
545c8e0a MF	62	#define CONFIG_CMD_DHCP
545c8e0a MF	63
545c8e0a MF	64
	65	#define CONFIG_MCFFEC
	66	#ifdef CONFIG_MCFFEC
545c8e0a	67	#define CONFIG_MII 1
0f3ba7e9	68	#define CONFIG_MII_INIT 1
6d0f6bcf JCPV	69	#define CONFIG_SYS_DISCOVER_PHY
	70	#define CONFIG_SYS_RX_ETH_BUFFER 8
	71	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	72	#define CONFIG_SYS_FEC0_PINMUX 0
	73	#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	74	#define CONFIG_SYS_FEC1_PINMUX 0
	75	#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
545c8e0a MF	76	#define MCFFEC_TOUT_LOOP 50000
545c8e0a MF	77	#define CONFIG_HAS_ETH1
6d0f6bcf JCPV	78	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	79	#ifndef CONFIG_SYS_DISCOVER_PHY
545c8e0a MF	80	#define FECDUPLEX FULL
	81	#define FECSPEED _100BASET
	82	#else
6d0f6bcf JCPV	83	#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	84	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
545c8e0a MF	85	#endif
	86	#endif
	87	#endif
	88
	89	/* I2C */
00f792e0 HS	90	#define CONFIG_SYS_I2C
	91	#define CONFIG_SYS_I2C_FSL
	92	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	93	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	94	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
6d0f6bcf JCPV	95	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	96	#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
	97	#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
	98	#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
545c8e0a	99
6d0f6bcf	100	#define CONFIG_SYS_LONGHELP /* undef to save memory */
545c8e0a MF	101
545c8e0a MF	102	#if (CONFIG_CMD_KGDB)
6d0f6bcf	103	# define CONFIG_SYS_CBSIZE 1024
545c8e0a	104	#else
6d0f6bcf	105	# define CONFIG_SYS_CBSIZE 256
545c8e0a	106	#endif
6d0f6bcf JCPV	107	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	108	#define CONFIG_SYS_MAXARGS 16
	109	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
545c8e0a	110
6d0f6bcf	111	#define CONFIG_SYS_LOAD_ADDR 0x800000
545c8e0a MF	112
	113	#define CONFIG_BOOTDELAY 5
	114	#define CONFIG_BOOTCOMMAND "bootm ffe40000"
6d0f6bcf JCPV	115	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	116	#define CONFIG_SYS_MEMTEST_END 0x380000
545c8e0a	117
0e8a7555 TL	118	#ifdef CONFIG_MCFFEC
	119	# define CONFIG_NET_RETRY_COUNT 5
	120	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	121	#endif /* FEC_ENET */
	122
	123	#define CONFIG_EXTRA_ENV_SETTINGS \
	124	"netdev=eth0\0" \
	125	"loadaddr=10000\0" \
	126	"uboot=u-boot.bin\0" \
	127	"load=tftp ${loadaddr} ${uboot}\0" \
	128	"upd=run load; run prog\0" \
	129	"prog=prot off ffe00000 ffe3ffff;" \
	130	"era ffe00000 ffe3ffff;" \
	131	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	132	"save\0" \
	133	""
	134
6d0f6bcf	135	#define CONFIG_SYS_CLK 150000000
545c8e0a MF	136
	137	/*
	138	* Low Level Configuration Settings
	139	* (address mappings, register initial values, etc.)
	140	* You should know what you are doing if you make changes here.
	141	*/
	142
6d0f6bcf	143	#define CONFIG_SYS_MBAR 0x40000000
545c8e0a MF	144
	145	/*-----------------------------------------------------------------------
	146	* Definitions for initial stack pointer and data area (in DPRAM)
	147	*/
6d0f6bcf	148	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	149	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	150	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	151	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
545c8e0a MF	152
	153	/*-----------------------------------------------------------------------
	154	* Start addresses for the final memory configuration
	155	* (Set up by the startup code)
6d0f6bcf	156	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
545c8e0a	157	*/
6d0f6bcf JCPV	158	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	159	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
012522fe	160	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
545c8e0a MF	161
545c8e0a MF	162	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	163	#define CONFIG_SYS_MONITOR_BASE 0x20000
545c8e0a	164	#else
6d0f6bcf	165	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
545c8e0a MF	166	#endif
545c8e0a MF	167
6d0f6bcf JCPV	168	#define CONFIG_SYS_MONITOR_LEN 0x20000
	169	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	170	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
545c8e0a MF	171
	172	/*
	173	* For booting Linux, the board info and command line data
	174	* have to be in the first 8 MB of memory, since this is
	175	* the maximum mapped by the Linux kernel during initialization ??
	176	*/
d6e4baf4 TL	177	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4 TL	178	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
545c8e0a MF	179
	180	/*-----------------------------------------------------------------------
	181	* FLASH organization
	182	*/
6d0f6bcf JCPV	183	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	184	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
	185	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
545c8e0a	186
6d0f6bcf	187	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	188	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf	189	#define CONFIG_SYS_FLASH_SIZE 0x200000
545c8e0a MF	190
	191	/*-----------------------------------------------------------------------
	192	* Cache Configuration
	193	*/
6d0f6bcf	194	#define CONFIG_SYS_CACHELINE_SIZE 16
545c8e0a	195
dd9f054e	196	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	197	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	198	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	199	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	200	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	201	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	202	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	203	CF_ACR_EN \| CF_ACR_SM_ALL)
	204	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	205	CF_CACR_DISD \| CF_CACR_INVI \| \
	206	CF_CACR_CEIB \| CF_CACR_DCM \| \
	207	CF_CACR_EUSP)
	208
545c8e0a MF	209	/*-----------------------------------------------------------------------
	210	* Memory bank definitions
	211	*/
012522fe TL	212	#define CONFIG_SYS_CS0_BASE 0xffe00000
	213	#define CONFIG_SYS_CS0_CTRL 0x00001980
	214	#define CONFIG_SYS_CS0_MASK 0x001F0001
545c8e0a	215
012522fe TL	216	#define CONFIG_SYS_CS1_BASE 0x30000000
	217	#define CONFIG_SYS_CS1_CTRL 0x00001900
	218	#define CONFIG_SYS_CS1_MASK 0x00070001
545c8e0a MF	219
	220	/*-----------------------------------------------------------------------
	221	* Port configuration
	222	*/
6d0f6bcf	223	#define CONFIG_SYS_FECI2C 0x0FA0
545c8e0a MF	224
545c8e0a MF	225	#endif /* _M5275EVB_H */