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545c8e0a MF |
1 | /* |
2 | * Configuation settings for the Motorola MC5275EVB board. | |
3 | * | |
4 | * By Arthur Shipkowski <art@videon-central.com> | |
5 | * Copyright (C) 2005 Videon Central, Inc. | |
6 | * | |
7 | * Based off of M5272C3 board code by Josef Baumgartner | |
8 | * <josef.baumgartner@telex.de> | |
9 | * | |
3765b3e7 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
545c8e0a MF |
11 | */ |
12 | ||
13 | /* | |
14 | * board/config.h - configuration options, board specific | |
15 | */ | |
16 | ||
17 | #ifndef _M5275EVB_H | |
18 | #define _M5275EVB_H | |
19 | ||
20 | /* | |
21 | * High Level Configuration Options | |
22 | * (easy to change) | |
23 | */ | |
545c8e0a MF |
24 | #define CONFIG_M5275EVB /* define board type */ |
25 | ||
26 | #define CONFIG_MCFTMR | |
27 | ||
28 | #define CONFIG_MCFUART | |
6d0f6bcf | 29 | #define CONFIG_SYS_UART_PORT (0) |
79e0799c | 30 | #define CONFIG_BAUDRATE 115200 |
545c8e0a MF |
31 | |
32 | /* Configuration for environment | |
33 | * Environment is embedded in u-boot in the second sector of the flash | |
34 | */ | |
35 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
36 | #define CONFIG_ENV_OFFSET 0x4000 |
37 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 38 | #define CONFIG_ENV_IS_IN_FLASH 1 |
545c8e0a | 39 | #else |
0e8d1586 JCPV |
40 | #define CONFIG_ENV_ADDR 0xffe04000 |
41 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 42 | #define CONFIG_ENV_IS_IN_FLASH 1 |
545c8e0a MF |
43 | #endif |
44 | ||
5296cb1d | 45 | #define LDS_BOARD_TEXT \ |
46 | . = DEFINED(env_offset) ? env_offset : .; \ | |
47 | common/env_embedded.o (.text); | |
48 | ||
545c8e0a MF |
49 | /* |
50 | * BOOTP options | |
51 | */ | |
52 | #define CONFIG_BOOTP_BOOTFILESIZE | |
53 | #define CONFIG_BOOTP_BOOTPATH | |
54 | #define CONFIG_BOOTP_GATEWAY | |
55 | #define CONFIG_BOOTP_HOSTNAME | |
56 | ||
57 | /* Available command configuration */ | |
545c8e0a | 58 | |
545c8e0a MF |
59 | #define CONFIG_MCFFEC |
60 | #ifdef CONFIG_MCFFEC | |
545c8e0a | 61 | #define CONFIG_MII 1 |
0f3ba7e9 | 62 | #define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
63 | #define CONFIG_SYS_DISCOVER_PHY |
64 | #define CONFIG_SYS_RX_ETH_BUFFER 8 | |
65 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
66 | #define CONFIG_SYS_FEC0_PINMUX 0 | |
67 | #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
68 | #define CONFIG_SYS_FEC1_PINMUX 0 | |
69 | #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE | |
545c8e0a MF |
70 | #define MCFFEC_TOUT_LOOP 50000 |
71 | #define CONFIG_HAS_ETH1 | |
6d0f6bcf JCPV |
72 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
73 | #ifndef CONFIG_SYS_DISCOVER_PHY | |
545c8e0a MF |
74 | #define FECDUPLEX FULL |
75 | #define FECSPEED _100BASET | |
76 | #else | |
6d0f6bcf JCPV |
77 | #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
78 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
545c8e0a MF |
79 | #endif |
80 | #endif | |
81 | #endif | |
82 | ||
83 | /* I2C */ | |
00f792e0 HS |
84 | #define CONFIG_SYS_I2C |
85 | #define CONFIG_SYS_I2C_FSL | |
86 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
87 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
88 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 | |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
90 | #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) | |
91 | #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) | |
92 | #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) | |
545c8e0a | 93 | |
6d0f6bcf | 94 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
545c8e0a MF |
95 | |
96 | #if (CONFIG_CMD_KGDB) | |
6d0f6bcf | 97 | # define CONFIG_SYS_CBSIZE 1024 |
545c8e0a | 98 | #else |
6d0f6bcf | 99 | # define CONFIG_SYS_CBSIZE 256 |
545c8e0a | 100 | #endif |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
102 | #define CONFIG_SYS_MAXARGS 16 | |
103 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
545c8e0a | 104 | |
6d0f6bcf | 105 | #define CONFIG_SYS_LOAD_ADDR 0x800000 |
545c8e0a | 106 | |
545c8e0a | 107 | #define CONFIG_BOOTCOMMAND "bootm ffe40000" |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_MEMTEST_START 0x400 |
109 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
545c8e0a | 110 | |
0e8a7555 TL |
111 | #ifdef CONFIG_MCFFEC |
112 | # define CONFIG_NET_RETRY_COUNT 5 | |
113 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
114 | #endif /* FEC_ENET */ | |
115 | ||
116 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
117 | "netdev=eth0\0" \ | |
118 | "loadaddr=10000\0" \ | |
119 | "uboot=u-boot.bin\0" \ | |
120 | "load=tftp ${loadaddr} ${uboot}\0" \ | |
121 | "upd=run load; run prog\0" \ | |
122 | "prog=prot off ffe00000 ffe3ffff;" \ | |
123 | "era ffe00000 ffe3ffff;" \ | |
124 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
125 | "save\0" \ | |
126 | "" | |
127 | ||
6d0f6bcf | 128 | #define CONFIG_SYS_CLK 150000000 |
545c8e0a MF |
129 | |
130 | /* | |
131 | * Low Level Configuration Settings | |
132 | * (address mappings, register initial values, etc.) | |
133 | * You should know what you are doing if you make changes here. | |
134 | */ | |
135 | ||
6d0f6bcf | 136 | #define CONFIG_SYS_MBAR 0x40000000 |
545c8e0a MF |
137 | |
138 | /*----------------------------------------------------------------------- | |
139 | * Definitions for initial stack pointer and data area (in DPRAM) | |
140 | */ | |
6d0f6bcf | 141 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 142 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 143 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 144 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
545c8e0a MF |
145 | |
146 | /*----------------------------------------------------------------------- | |
147 | * Start addresses for the final memory configuration | |
148 | * (Set up by the startup code) | |
6d0f6bcf | 149 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
545c8e0a | 150 | */ |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
152 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
012522fe | 153 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
545c8e0a MF |
154 | |
155 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 156 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
545c8e0a | 157 | #else |
6d0f6bcf | 158 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
545c8e0a MF |
159 | #endif |
160 | ||
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
162 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
163 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
545c8e0a MF |
164 | |
165 | /* | |
166 | * For booting Linux, the board info and command line data | |
167 | * have to be in the first 8 MB of memory, since this is | |
168 | * the maximum mapped by the Linux kernel during initialization ?? | |
169 | */ | |
d6e4baf4 TL |
170 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
171 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) | |
545c8e0a MF |
172 | |
173 | /*----------------------------------------------------------------------- | |
174 | * FLASH organization | |
175 | */ | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
177 | #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ | |
178 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
545c8e0a | 179 | |
6d0f6bcf | 180 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 181 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf | 182 | #define CONFIG_SYS_FLASH_SIZE 0x200000 |
545c8e0a MF |
183 | |
184 | /*----------------------------------------------------------------------- | |
185 | * Cache Configuration | |
186 | */ | |
6d0f6bcf | 187 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
545c8e0a | 188 | |
dd9f054e | 189 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 190 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 191 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 192 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
193 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
194 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
195 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
196 | CF_ACR_EN | CF_ACR_SM_ALL) | |
197 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
198 | CF_CACR_DISD | CF_CACR_INVI | \ | |
199 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
200 | CF_CACR_EUSP) | |
201 | ||
545c8e0a MF |
202 | /*----------------------------------------------------------------------- |
203 | * Memory bank definitions | |
204 | */ | |
012522fe TL |
205 | #define CONFIG_SYS_CS0_BASE 0xffe00000 |
206 | #define CONFIG_SYS_CS0_CTRL 0x00001980 | |
207 | #define CONFIG_SYS_CS0_MASK 0x001F0001 | |
545c8e0a | 208 | |
012522fe TL |
209 | #define CONFIG_SYS_CS1_BASE 0x30000000 |
210 | #define CONFIG_SYS_CS1_CTRL 0x00001900 | |
211 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
545c8e0a MF |
212 | |
213 | /*----------------------------------------------------------------------- | |
214 | * Port configuration | |
215 | */ | |
6d0f6bcf | 216 | #define CONFIG_SYS_FECI2C 0x0FA0 |
545c8e0a MF |
217 | |
218 | #endif /* _M5275EVB_H */ |