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545c8e0a MF |
1 | /* |
2 | * Configuation settings for the Motorola MC5275EVB board. | |
3 | * | |
4 | * By Arthur Shipkowski <art@videon-central.com> | |
5 | * Copyright (C) 2005 Videon Central, Inc. | |
6 | * | |
7 | * Based off of M5272C3 board code by Josef Baumgartner | |
8 | * <josef.baumgartner@telex.de> | |
9 | * | |
3765b3e7 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
545c8e0a MF |
11 | */ |
12 | ||
13 | /* | |
14 | * board/config.h - configuration options, board specific | |
15 | */ | |
16 | ||
17 | #ifndef _M5275EVB_H | |
18 | #define _M5275EVB_H | |
19 | ||
20 | /* | |
21 | * High Level Configuration Options | |
22 | * (easy to change) | |
23 | */ | |
545c8e0a MF |
24 | #define CONFIG_M5275EVB /* define board type */ |
25 | ||
26 | #define CONFIG_MCFTMR | |
27 | ||
28 | #define CONFIG_MCFUART | |
6d0f6bcf | 29 | #define CONFIG_SYS_UART_PORT (0) |
545c8e0a MF |
30 | |
31 | /* Configuration for environment | |
32 | * Environment is embedded in u-boot in the second sector of the flash | |
33 | */ | |
34 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
35 | #define CONFIG_ENV_OFFSET 0x4000 |
36 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 37 | #define CONFIG_ENV_IS_IN_FLASH 1 |
545c8e0a | 38 | #else |
0e8d1586 JCPV |
39 | #define CONFIG_ENV_ADDR 0xffe04000 |
40 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 41 | #define CONFIG_ENV_IS_IN_FLASH 1 |
545c8e0a MF |
42 | #endif |
43 | ||
5296cb1d | 44 | #define LDS_BOARD_TEXT \ |
45 | . = DEFINED(env_offset) ? env_offset : .; \ | |
46 | common/env_embedded.o (.text); | |
47 | ||
545c8e0a MF |
48 | /* |
49 | * BOOTP options | |
50 | */ | |
51 | #define CONFIG_BOOTP_BOOTFILESIZE | |
52 | #define CONFIG_BOOTP_BOOTPATH | |
53 | #define CONFIG_BOOTP_GATEWAY | |
54 | #define CONFIG_BOOTP_HOSTNAME | |
55 | ||
56 | /* Available command configuration */ | |
545c8e0a | 57 | |
545c8e0a MF |
58 | #define CONFIG_MCFFEC |
59 | #ifdef CONFIG_MCFFEC | |
545c8e0a | 60 | #define CONFIG_MII 1 |
0f3ba7e9 | 61 | #define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
62 | #define CONFIG_SYS_DISCOVER_PHY |
63 | #define CONFIG_SYS_RX_ETH_BUFFER 8 | |
64 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
65 | #define CONFIG_SYS_FEC0_PINMUX 0 | |
66 | #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
67 | #define CONFIG_SYS_FEC1_PINMUX 0 | |
68 | #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE | |
545c8e0a MF |
69 | #define MCFFEC_TOUT_LOOP 50000 |
70 | #define CONFIG_HAS_ETH1 | |
6d0f6bcf JCPV |
71 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
72 | #ifndef CONFIG_SYS_DISCOVER_PHY | |
545c8e0a MF |
73 | #define FECDUPLEX FULL |
74 | #define FECSPEED _100BASET | |
75 | #else | |
6d0f6bcf JCPV |
76 | #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
77 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
545c8e0a MF |
78 | #endif |
79 | #endif | |
80 | #endif | |
81 | ||
82 | /* I2C */ | |
00f792e0 HS |
83 | #define CONFIG_SYS_I2C |
84 | #define CONFIG_SYS_I2C_FSL | |
85 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
86 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
87 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 | |
6d0f6bcf JCPV |
88 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
89 | #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) | |
90 | #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) | |
91 | #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) | |
545c8e0a | 92 | |
6d0f6bcf | 93 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
545c8e0a MF |
94 | |
95 | #if (CONFIG_CMD_KGDB) | |
6d0f6bcf | 96 | # define CONFIG_SYS_CBSIZE 1024 |
545c8e0a | 97 | #else |
6d0f6bcf | 98 | # define CONFIG_SYS_CBSIZE 256 |
545c8e0a | 99 | #endif |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
101 | #define CONFIG_SYS_MAXARGS 16 | |
102 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
545c8e0a | 103 | |
6d0f6bcf | 104 | #define CONFIG_SYS_LOAD_ADDR 0x800000 |
545c8e0a | 105 | |
545c8e0a | 106 | #define CONFIG_BOOTCOMMAND "bootm ffe40000" |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_MEMTEST_START 0x400 |
108 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
545c8e0a | 109 | |
0e8a7555 TL |
110 | #ifdef CONFIG_MCFFEC |
111 | # define CONFIG_NET_RETRY_COUNT 5 | |
112 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
113 | #endif /* FEC_ENET */ | |
114 | ||
115 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
116 | "netdev=eth0\0" \ | |
117 | "loadaddr=10000\0" \ | |
118 | "uboot=u-boot.bin\0" \ | |
119 | "load=tftp ${loadaddr} ${uboot}\0" \ | |
120 | "upd=run load; run prog\0" \ | |
121 | "prog=prot off ffe00000 ffe3ffff;" \ | |
122 | "era ffe00000 ffe3ffff;" \ | |
123 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
124 | "save\0" \ | |
125 | "" | |
126 | ||
6d0f6bcf | 127 | #define CONFIG_SYS_CLK 150000000 |
545c8e0a MF |
128 | |
129 | /* | |
130 | * Low Level Configuration Settings | |
131 | * (address mappings, register initial values, etc.) | |
132 | * You should know what you are doing if you make changes here. | |
133 | */ | |
134 | ||
6d0f6bcf | 135 | #define CONFIG_SYS_MBAR 0x40000000 |
545c8e0a MF |
136 | |
137 | /*----------------------------------------------------------------------- | |
138 | * Definitions for initial stack pointer and data area (in DPRAM) | |
139 | */ | |
6d0f6bcf | 140 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 141 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 142 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 143 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
545c8e0a MF |
144 | |
145 | /*----------------------------------------------------------------------- | |
146 | * Start addresses for the final memory configuration | |
147 | * (Set up by the startup code) | |
6d0f6bcf | 148 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
545c8e0a | 149 | */ |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
151 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
012522fe | 152 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
545c8e0a MF |
153 | |
154 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 155 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
545c8e0a | 156 | #else |
6d0f6bcf | 157 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
545c8e0a MF |
158 | #endif |
159 | ||
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
161 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
162 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
545c8e0a MF |
163 | |
164 | /* | |
165 | * For booting Linux, the board info and command line data | |
166 | * have to be in the first 8 MB of memory, since this is | |
167 | * the maximum mapped by the Linux kernel during initialization ?? | |
168 | */ | |
d6e4baf4 TL |
169 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
170 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) | |
545c8e0a MF |
171 | |
172 | /*----------------------------------------------------------------------- | |
173 | * FLASH organization | |
174 | */ | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
176 | #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ | |
177 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
545c8e0a | 178 | |
6d0f6bcf | 179 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 180 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf | 181 | #define CONFIG_SYS_FLASH_SIZE 0x200000 |
545c8e0a MF |
182 | |
183 | /*----------------------------------------------------------------------- | |
184 | * Cache Configuration | |
185 | */ | |
6d0f6bcf | 186 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
545c8e0a | 187 | |
dd9f054e | 188 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 189 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 190 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 191 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
192 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
193 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
194 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
195 | CF_ACR_EN | CF_ACR_SM_ALL) | |
196 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
197 | CF_CACR_DISD | CF_CACR_INVI | \ | |
198 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
199 | CF_CACR_EUSP) | |
200 | ||
545c8e0a MF |
201 | /*----------------------------------------------------------------------- |
202 | * Memory bank definitions | |
203 | */ | |
012522fe TL |
204 | #define CONFIG_SYS_CS0_BASE 0xffe00000 |
205 | #define CONFIG_SYS_CS0_CTRL 0x00001980 | |
206 | #define CONFIG_SYS_CS0_MASK 0x001F0001 | |
545c8e0a | 207 | |
012522fe TL |
208 | #define CONFIG_SYS_CS1_BASE 0x30000000 |
209 | #define CONFIG_SYS_CS1_CTRL 0x00001900 | |
210 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
545c8e0a MF |
211 | |
212 | /*----------------------------------------------------------------------- | |
213 | * Port configuration | |
214 | */ | |
6d0f6bcf | 215 | #define CONFIG_SYS_FECI2C 0x0FA0 |
545c8e0a MF |
216 | |
217 | #endif /* _M5275EVB_H */ |