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bf9e3b38 WD |
1 | /* |
2 | * Configuation settings for the Motorola MC5282EVB board. | |
3 | * | |
4 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
bf9e3b38 WD |
7 | */ |
8 | ||
9 | /* | |
10 | * board/config.h - configuration options, board specific | |
11 | */ | |
12 | ||
4e5ca3eb WD |
13 | #ifndef _CONFIG_M5282EVB_H |
14 | #define _CONFIG_M5282EVB_H | |
15 | ||
bf9e3b38 WD |
16 | /* |
17 | * High Level Configuration Options | |
18 | * (easy to change) | |
19 | */ | |
f28e1bd9 | 20 | #define CONFIG_MCFTMR |
bf9e3b38 | 21 | |
f28e1bd9 | 22 | #define CONFIG_MCFUART |
6d0f6bcf | 23 | #define CONFIG_SYS_UART_PORT (0) |
79e0799c | 24 | #define CONFIG_BAUDRATE 115200 |
4e5ca3eb | 25 | |
f28e1bd9 | 26 | #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ |
bf9e3b38 WD |
27 | |
28 | /* Configuration for environment | |
29 | * Environment is embedded in u-boot in the second sector of the flash | |
30 | */ | |
0e8d1586 JCPV |
31 | #define CONFIG_ENV_ADDR 0xffe04000 |
32 | #define CONFIG_ENV_SIZE 0x2000 | |
5a1aceb0 | 33 | #define CONFIG_ENV_IS_IN_FLASH 1 |
bf9e3b38 | 34 | |
5296cb1d | 35 | #define LDS_BOARD_TEXT \ |
36 | . = DEFINED(env_offset) ? env_offset : .; \ | |
37 | common/env_embedded.o (.text*); | |
38 | ||
659e2f67 JL |
39 | /* |
40 | * BOOTP options | |
41 | */ | |
42 | #define CONFIG_BOOTP_BOOTFILESIZE | |
43 | #define CONFIG_BOOTP_BOOTPATH | |
44 | #define CONFIG_BOOTP_GATEWAY | |
45 | #define CONFIG_BOOTP_HOSTNAME | |
46 | ||
8353e139 JL |
47 | /* |
48 | * Command line configuration. | |
49 | */ | |
8353e139 | 50 | |
f28e1bd9 TL |
51 | #define CONFIG_MCFFEC |
52 | #ifdef CONFIG_MCFFEC | |
f28e1bd9 | 53 | # define CONFIG_MII 1 |
0f3ba7e9 | 54 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
55 | # define CONFIG_SYS_DISCOVER_PHY |
56 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
57 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
f28e1bd9 | 58 | |
6d0f6bcf JCPV |
59 | # define CONFIG_SYS_FEC0_PINMUX 0 |
60 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 61 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
62 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
63 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
f28e1bd9 TL |
64 | # define FECDUPLEX FULL |
65 | # define FECSPEED _100BASET | |
66 | # else | |
6d0f6bcf JCPV |
67 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
68 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
f28e1bd9 | 69 | # endif |
6d0f6bcf | 70 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
f28e1bd9 | 71 | #endif |
bf9e3b38 | 72 | |
f28e1bd9 | 73 | #ifdef CONFIG_MCFFEC |
f28e1bd9 TL |
74 | # define CONFIG_IPADDR 192.162.1.2 |
75 | # define CONFIG_NETMASK 255.255.255.0 | |
76 | # define CONFIG_SERVERIP 192.162.1.1 | |
77 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
f28e1bd9 TL |
78 | #endif /* CONFIG_MCFFEC */ |
79 | ||
4cb4e654 | 80 | #define CONFIG_HOSTNAME M5282EVB |
f28e1bd9 TL |
81 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
82 | "netdev=eth0\0" \ | |
83 | "loadaddr=10000\0" \ | |
84 | "u-boot=u-boot.bin\0" \ | |
85 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
86 | "upd=run load; run prog\0" \ | |
87 | "prog=prot off ffe00000 ffe3ffff;" \ | |
88 | "era ffe00000 ffe3ffff;" \ | |
89 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
90 | "save\0" \ | |
91 | "" | |
bf9e3b38 | 92 | |
6d0f6bcf | 93 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
bf9e3b38 | 94 | |
8353e139 | 95 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 96 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
bf9e3b38 | 97 | #else |
6d0f6bcf | 98 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
bf9e3b38 | 99 | #endif |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
101 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
102 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
bf9e3b38 | 103 | |
6d0f6bcf | 104 | #define CONFIG_SYS_LOAD_ADDR 0x20000 |
bf9e3b38 | 105 | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_MEMTEST_START 0x400 |
107 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
bf9e3b38 | 108 | |
6d0f6bcf | 109 | #define CONFIG_SYS_CLK 64000000 |
bf9e3b38 | 110 | |
f28e1bd9 TL |
111 | /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ |
112 | ||
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ |
114 | #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ | |
bf9e3b38 WD |
115 | |
116 | /* | |
117 | * Low Level Configuration Settings | |
118 | * (address mappings, register initial values, etc.) | |
119 | * You should know what you are doing if you make changes here. | |
120 | */ | |
6d0f6bcf | 121 | #define CONFIG_SYS_MBAR 0x40000000 |
bf9e3b38 | 122 | |
bf9e3b38 WD |
123 | /*----------------------------------------------------------------------- |
124 | * Definitions for initial stack pointer and data area (in DPRAM) | |
125 | */ | |
6d0f6bcf | 126 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 127 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 128 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 129 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
bf9e3b38 WD |
130 | |
131 | /*----------------------------------------------------------------------- | |
132 | * Start addresses for the final memory configuration | |
133 | * (Set up by the startup code) | |
6d0f6bcf | 134 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
bf9e3b38 | 135 | */ |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
137 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
012522fe | 138 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 |
140 | #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 | |
bf9e3b38 WD |
141 | |
142 | /* If M5282 port is fully implemented the monitor base will be behind | |
143 | * the vector table. */ | |
14d0a02a | 144 | #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) |
6d0f6bcf | 145 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
f28e1bd9 | 146 | #else |
14d0a02a | 147 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ |
f28e1bd9 | 148 | #endif |
bf9e3b38 | 149 | |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
151 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
152 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
bf9e3b38 | 153 | |
bf9e3b38 WD |
154 | /* |
155 | * For booting Linux, the board info and command line data | |
156 | * have to be in the first 8 MB of memory, since this is | |
157 | * the maximum mapped by the Linux kernel during initialization ?? | |
158 | */ | |
6d0f6bcf | 159 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
bf9e3b38 WD |
160 | |
161 | /*----------------------------------------------------------------------- | |
162 | * FLASH organization | |
163 | */ | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_FLASH_CFI |
165 | #ifdef CONFIG_SYS_FLASH_CFI | |
f28e1bd9 | 166 | |
00b1883a | 167 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
168 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
169 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
170 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
171 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
172 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
173 | # define CONFIG_SYS_FLASH_CHECKSUM | |
174 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
f28e1bd9 | 175 | #endif |
bf9e3b38 WD |
176 | |
177 | /*----------------------------------------------------------------------- | |
178 | * Cache Configuration | |
179 | */ | |
6d0f6bcf | 180 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
bf9e3b38 | 181 | |
dd9f054e | 182 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 183 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 184 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 185 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
186 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) |
187 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
188 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
189 | CF_ACR_EN | CF_ACR_SM_ALL) | |
190 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ | |
191 | CF_CACR_CEIB | CF_CACR_DBWE | \ | |
192 | CF_CACR_EUSP) | |
193 | ||
bf9e3b38 WD |
194 | /*----------------------------------------------------------------------- |
195 | * Memory bank definitions | |
196 | */ | |
012522fe TL |
197 | #define CONFIG_SYS_CS0_BASE 0xFFE00000 |
198 | #define CONFIG_SYS_CS0_CTRL 0x00001980 | |
199 | #define CONFIG_SYS_CS0_MASK 0x001F0001 | |
200 | ||
bf9e3b38 WD |
201 | /*----------------------------------------------------------------------- |
202 | * Port configuration | |
203 | */ | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ |
205 | #define CONFIG_SYS_PADDR 0x0000000 | |
206 | #define CONFIG_SYS_PADAT 0x0000000 | |
207 | ||
208 | #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ | |
209 | #define CONFIG_SYS_PBDDR 0x0000000 | |
210 | #define CONFIG_SYS_PBDAT 0x0000000 | |
211 | ||
212 | #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ | |
213 | #define CONFIG_SYS_PCDDR 0x0000000 | |
214 | #define CONFIG_SYS_PCDAT 0x0000000 | |
215 | ||
216 | #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ | |
217 | #define CONFIG_SYS_PCDDR 0x0000000 | |
218 | #define CONFIG_SYS_PCDAT 0x0000000 | |
219 | ||
220 | #define CONFIG_SYS_PEHLPAR 0xC0 | |
221 | #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ | |
222 | #define CONFIG_SYS_DDRUA 0x05 | |
223 | #define CONFIG_SYS_PJPAR 0xFF | |
4e5ca3eb | 224 | |
f28e1bd9 | 225 | #endif /* _CONFIG_M5282EVB_H */ |