[thirdparty/u-boot.git] / include / configs / M53017EVB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for the Freescale MCF53017EVB.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M53017EVB_H
#define _M53017EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT		5000

#define CONFIG_SYS_UNIFY_CACHE

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_TX_ETH_BUFFER	8
#	define CONFIG_SYS_FEC_BUF_USE_SRAM
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#	define CONFIG_HAS_ETH1

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_PINMUX	0
#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
#	define MCFFEC_TOUT_LOOP		50000

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_CNT		(0x8000)
#define CONFIG_SYS_RTC_SETUP		(RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

#define CONFIG_UDP_CHECKSUM

#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		"M53017"
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 3ffff;"		\
	"era 0 3ffff;"				\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */

#define CONFIG_SYS_LOAD_ADDR	0x40010000

#define CONFIG_SYS_CLK		80000000
#define CONFIG_SYS_CPU_CLK	CONFIG_SYS_CLK * 3

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x20000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x80010000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_SPANSION_S29WS_N	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#endif

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text*)

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
					 CF_CACR_DCM_P)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash
 * CS1 - Ext SRAM
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0

#define CONFIG_SYS_CS1_BASE		0xC0000000
#define CONFIG_SYS_CS1_MASK		0x00070001
#define CONFIG_SYS_CS1_CTRL		0x00001FA0

#endif				/* _M53017EVB_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
536e7dac TL	2	/*
	3	* Configuation settings for the Freescale MCF53017EVB.
	4	*
	5	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
536e7dac TL	7	*/
	8
	9	/*
	10	* board/config.h - configuration options, board specific
	11	*/
	12
	13	#ifndef _M53017EVB_H
	14	#define _M53017EVB_H
	15
	16	/*
	17	* High Level Configuration Options
	18	* (easy to change)
	19	*/
536e7dac TL	20
	21	#define CONFIG_MCFUART
	22	#define CONFIG_SYS_UART_PORT (0)
536e7dac TL	23
	24	#undef CONFIG_WATCHDOG
	25	#define CONFIG_WATCHDOG_TIMEOUT 5000
	26
536e7dac TL	27	#define CONFIG_SYS_UNIFY_CACHE
	28
	29	#define CONFIG_MCFFEC
	30	#ifdef CONFIG_MCFFEC
536e7dac TL	31	# define CONFIG_MII_INIT 1
	32	# define CONFIG_SYS_DISCOVER_PHY
	33	# define CONFIG_SYS_RX_ETH_BUFFER 8
9e8e9270 TL	34	# define CONFIG_SYS_TX_ETH_BUFFER 8
9e8e9270 TL	35	# define CONFIG_SYS_FEC_BUF_USE_SRAM
536e7dac TL	36	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	37	# define CONFIG_HAS_ETH1
	38
	39	# define CONFIG_SYS_FEC0_PINMUX 0
	40	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	41	# define CONFIG_SYS_FEC1_PINMUX 0
	42	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
	43	# define MCFFEC_TOUT_LOOP 50000
052c0891	44
536e7dac TL	45	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
	46	# ifndef CONFIG_SYS_DISCOVER_PHY
	47	# define FECDUPLEX FULL
	48	# define FECSPEED _100BASET
	49	# else
	50	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	51	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	52	# endif
	53	# endif /* CONFIG_SYS_DISCOVER_PHY */
	54	#endif
	55
	56	#define CONFIG_MCFRTC
	57	#undef RTC_DEBUG
	58	#define CONFIG_SYS_RTC_CNT (0x8000)
	59	#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP \| RTC_OCEN_CLKEN)
	60
	61	/* Timer */
	62	#define CONFIG_MCFTMR
	63	#undef CONFIG_MCFPIT
	64
	65	/* I2C */
00f792e0 HS	66	#define CONFIG_SYS_I2C
	67	#define CONFIG_SYS_I2C_FSL
	68	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	69	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	70	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
536e7dac TL	71	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
536e7dac TL	72
536e7dac TL	73	#define CONFIG_UDP_CHECKSUM
	74
	75	#ifdef CONFIG_MCFFEC
536e7dac TL	76	# define CONFIG_IPADDR 192.162.1.2
	77	# define CONFIG_NETMASK 255.255.255.0
	78	# define CONFIG_SERVERIP 192.162.1.1
	79	# define CONFIG_GATEWAYIP 192.162.1.1
536e7dac TL	80	#endif /* FEC_ENET */
536e7dac TL	81
5bc0543d	82	#define CONFIG_HOSTNAME "M53017"
536e7dac TL	83	#define CONFIG_EXTRA_ENV_SETTINGS \
	84	"netdev=eth0\0" \
	85	"loadaddr=40010000\0" \
	86	"u-boot=u-boot.bin\0" \
	87	"load=tftp ${loadaddr) ${u-boot}\0" \
	88	"upd=run load; run prog\0" \
	89	"prog=prot off 0 3ffff;" \
	90	"era 0 3ffff;" \
	91	"cp.b ${loadaddr} 0 ${filesize};" \
	92	"save\0" \
	93	""
	94
	95	#define CONFIG_PRAM 512 /* 512 KB */
536e7dac	96
536e7dac TL	97	#define CONFIG_SYS_LOAD_ADDR 0x40010000
536e7dac TL	98
536e7dac TL	99	#define CONFIG_SYS_CLK 80000000
	100	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
	101
	102	#define CONFIG_SYS_MBAR 0xFC000000
	103
	104	/*
	105	* Low Level Configuration Settings
	106	* (address mappings, register initial values, etc.)
	107	* You should know what you are doing if you make changes here.
	108	*/
	109	/*
	110	* Definitions for initial stack pointer and data area (in DPRAM)
	111	*/
	112	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	113	#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
9e8e9270	114	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	115	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
536e7dac TL	116	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	117
	118	/*
	119	* Start addresses for the final memory configuration
	120	* (Set up by the startup code)
	121	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
	122	*/
	123	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	124	#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
	125	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	126	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
9e8e9270	127	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
536e7dac TL	128	#define CONFIG_SYS_SDRAM_EMOD 0x80010000
	129	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
	130
	131	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	132	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	133
	134	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	135	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	136
	137	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	138	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	139
	140	/*
	141	* For booting Linux, the board info and command line data
	142	* have to be in the first 8 MB of memory, since this is
	143	* the maximum mapped by the Linux kernel during initialization ??
	144	*/
	145	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	146	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
536e7dac TL	147
	148	/*-----------------------------------------------------------------------
	149	* FLASH organization
	150	*/
536e7dac	151	#ifdef CONFIG_SYS_FLASH_CFI
bbf6bbff	152	# define CONFIG_FLASH_SPANSION_S29WS_N 1
4567c7bf	153	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
536e7dac TL	154	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	155	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	156	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
536e7dac TL	157	#endif
	158
	159	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	160
	161	/* Configuration for environment
	162	* Environment is embedded in u-boot in the second sector of the flash
	163	*/
536e7dac	164
5296cb1d	165	#define LDS_BOARD_TEXT \
5296cb1d	166	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d	167	env/embedded.o(.text*)
5296cb1d	168
536e7dac TL	169	/*-----------------------------------------------------------------------
	170	* Cache Configuration
	171	*/
	172	#define CONFIG_SYS_CACHELINE_SIZE 16
	173
dd9f054e	174	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	175	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	176	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	177	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	178	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
	179	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	180	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	181	CF_ACR_EN \| CF_ACR_SM_ALL)
	182	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC \| CF_CACR_CINVA \| \
	183	CF_CACR_DCM_P)
	184
536e7dac TL	185	/*-----------------------------------------------------------------------
	186	* Chipselect bank definitions
	187	*/
	188	/*
	189	* CS0 - NOR Flash
	190	* CS1 - Ext SRAM
	191	* CS2 - Available
	192	* CS3 - Available
	193	* CS4 - Available
	194	* CS5 - Available
	195	*/
	196	#define CONFIG_SYS_CS0_BASE 0
	197	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	198	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	199
	200	#define CONFIG_SYS_CS1_BASE 0xC0000000
	201	#define CONFIG_SYS_CS1_MASK 0x00070001
	202	#define CONFIG_SYS_CS1_CTRL 0x00001FA0
	203
	204	#endif /* _M53017EVB_H */