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536e7dac TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF53017EVB. | |
3 | * | |
4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
536e7dac TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M53017EVB_H | |
15 | #define _M53017EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
21 | #define CONFIG_MCF5301x /* define processor family */ | |
22 | #define CONFIG_M53015 /* define processor type */ | |
23 | ||
24 | #define CONFIG_MCFUART | |
25 | #define CONFIG_SYS_UART_PORT (0) | |
26 | #define CONFIG_BAUDRATE 115200 | |
536e7dac TL |
27 | |
28 | #undef CONFIG_WATCHDOG | |
29 | #define CONFIG_WATCHDOG_TIMEOUT 5000 | |
30 | ||
31 | /* Command line configuration */ | |
32 | #include <config_cmd_default.h> | |
33 | ||
34 | #define CONFIG_CMD_CACHE | |
35 | #define CONFIG_CMD_DATE | |
36 | #define CONFIG_CMD_ELF | |
37 | #define CONFIG_CMD_FLASH | |
38 | #undef CONFIG_CMD_I2C | |
39 | #define CONFIG_CMD_MEMORY | |
40 | #define CONFIG_CMD_MISC | |
41 | #define CONFIG_CMD_MII | |
42 | #define CONFIG_CMD_NET | |
43 | #define CONFIG_CMD_PING | |
44 | #define CONFIG_CMD_REGINFO | |
45 | ||
46 | #define CONFIG_SYS_UNIFY_CACHE | |
47 | ||
48 | #define CONFIG_MCFFEC | |
49 | #ifdef CONFIG_MCFFEC | |
536e7dac TL |
50 | # define CONFIG_MII 1 |
51 | # define CONFIG_MII_INIT 1 | |
52 | # define CONFIG_SYS_DISCOVER_PHY | |
53 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
9e8e9270 TL |
54 | # define CONFIG_SYS_TX_ETH_BUFFER 8 |
55 | # define CONFIG_SYS_FEC_BUF_USE_SRAM | |
536e7dac TL |
56 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
57 | # define CONFIG_HAS_ETH1 | |
58 | ||
59 | # define CONFIG_SYS_FEC0_PINMUX 0 | |
60 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
61 | # define CONFIG_SYS_FEC1_PINMUX 0 | |
62 | # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE | |
63 | # define MCFFEC_TOUT_LOOP 50000 | |
052c0891 TL |
64 | |
65 | # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2" | |
66 | ||
536e7dac TL |
67 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
68 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
69 | # define FECDUPLEX FULL | |
70 | # define FECSPEED _100BASET | |
71 | # else | |
72 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
73 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
74 | # endif | |
75 | # endif /* CONFIG_SYS_DISCOVER_PHY */ | |
76 | #endif | |
77 | ||
78 | #define CONFIG_MCFRTC | |
79 | #undef RTC_DEBUG | |
80 | #define CONFIG_SYS_RTC_CNT (0x8000) | |
81 | #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) | |
82 | ||
83 | /* Timer */ | |
84 | #define CONFIG_MCFTMR | |
85 | #undef CONFIG_MCFPIT | |
86 | ||
87 | /* I2C */ | |
00f792e0 HS |
88 | #define CONFIG_SYS_I2C |
89 | #define CONFIG_SYS_I2C_FSL | |
90 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
91 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
92 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
536e7dac TL |
93 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
94 | ||
95 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
96 | #define CONFIG_UDP_CHECKSUM | |
97 | ||
98 | #ifdef CONFIG_MCFFEC | |
99 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 | |
100 | # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 | |
101 | # define CONFIG_IPADDR 192.162.1.2 | |
102 | # define CONFIG_NETMASK 255.255.255.0 | |
103 | # define CONFIG_SERVERIP 192.162.1.1 | |
104 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
105 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
106 | #endif /* FEC_ENET */ | |
107 | ||
108 | #define CONFIG_HOSTNAME M53017 | |
109 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
110 | "netdev=eth0\0" \ | |
111 | "loadaddr=40010000\0" \ | |
112 | "u-boot=u-boot.bin\0" \ | |
113 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
114 | "upd=run load; run prog\0" \ | |
115 | "prog=prot off 0 3ffff;" \ | |
116 | "era 0 3ffff;" \ | |
117 | "cp.b ${loadaddr} 0 ${filesize};" \ | |
118 | "save\0" \ | |
119 | "" | |
120 | ||
121 | #define CONFIG_PRAM 512 /* 512 KB */ | |
122 | #define CONFIG_SYS_PROMPT "-> " | |
123 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
124 | ||
125 | #ifdef CONFIG_CMD_KGDB | |
126 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
127 | #else | |
128 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
129 | #endif | |
130 | ||
131 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
132 | #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ | |
133 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ | |
134 | #define CONFIG_SYS_LOAD_ADDR 0x40010000 | |
135 | ||
536e7dac TL |
136 | #define CONFIG_SYS_CLK 80000000 |
137 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 | |
138 | ||
139 | #define CONFIG_SYS_MBAR 0xFC000000 | |
140 | ||
141 | /* | |
142 | * Low Level Configuration Settings | |
143 | * (address mappings, register initial values, etc.) | |
144 | * You should know what you are doing if you make changes here. | |
145 | */ | |
146 | /* | |
147 | * Definitions for initial stack pointer and data area (in DPRAM) | |
148 | */ | |
149 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 | |
553f0982 | 150 | #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ |
9e8e9270 | 151 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 152 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
536e7dac TL |
153 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
154 | ||
155 | /* | |
156 | * Start addresses for the final memory configuration | |
157 | * (Set up by the startup code) | |
158 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
159 | */ | |
160 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
161 | #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ | |
162 | #define CONFIG_SYS_SDRAM_CFG1 0x43711630 | |
163 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
9e8e9270 | 164 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 |
536e7dac TL |
165 | #define CONFIG_SYS_SDRAM_EMOD 0x80010000 |
166 | #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 | |
167 | ||
168 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
169 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
170 | ||
171 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
172 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
173 | ||
174 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
175 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
176 | ||
177 | /* | |
178 | * For booting Linux, the board info and command line data | |
179 | * have to be in the first 8 MB of memory, since this is | |
180 | * the maximum mapped by the Linux kernel during initialization ?? | |
181 | */ | |
182 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) | |
d6e4baf4 | 183 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
536e7dac TL |
184 | |
185 | /*----------------------------------------------------------------------- | |
186 | * FLASH organization | |
187 | */ | |
188 | #define CONFIG_SYS_FLASH_CFI | |
189 | #ifdef CONFIG_SYS_FLASH_CFI | |
190 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
bbf6bbff TL |
191 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
192 | # define CONFIG_FLASH_SPANSION_S29WS_N 1 | |
4567c7bf | 193 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
536e7dac TL |
194 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
195 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
196 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
197 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
198 | #endif | |
199 | ||
200 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
201 | ||
202 | /* Configuration for environment | |
203 | * Environment is embedded in u-boot in the second sector of the flash | |
204 | */ | |
205 | #define CONFIG_ENV_OFFSET 0x8000 | |
206 | #define CONFIG_ENV_SIZE 0x1000 | |
207 | #define CONFIG_ENV_SECT_SIZE 0x8000 | |
208 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
209 | ||
210 | /*----------------------------------------------------------------------- | |
211 | * Cache Configuration | |
212 | */ | |
213 | #define CONFIG_SYS_CACHELINE_SIZE 16 | |
214 | ||
dd9f054e | 215 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 216 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 217 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 218 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
219 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
220 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
221 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
222 | CF_ACR_EN | CF_ACR_SM_ALL) | |
223 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ | |
224 | CF_CACR_DCM_P) | |
225 | ||
536e7dac TL |
226 | /*----------------------------------------------------------------------- |
227 | * Chipselect bank definitions | |
228 | */ | |
229 | /* | |
230 | * CS0 - NOR Flash | |
231 | * CS1 - Ext SRAM | |
232 | * CS2 - Available | |
233 | * CS3 - Available | |
234 | * CS4 - Available | |
235 | * CS5 - Available | |
236 | */ | |
237 | #define CONFIG_SYS_CS0_BASE 0 | |
238 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
239 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
240 | ||
241 | #define CONFIG_SYS_CS1_BASE 0xC0000000 | |
242 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
243 | #define CONFIG_SYS_CS1_CTRL 0x00001FA0 | |
244 | ||
245 | #endif /* _M53017EVB_H */ |