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8e585f02 TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF5329 FireEngine board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
8e585f02 TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M5329EVB_H | |
15 | #define _M5329EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
21 | #define CONFIG_MCF532x /* define processor family */ | |
22 | #define CONFIG_M5329 /* define processor type */ | |
23 | ||
9998bd37 | 24 | #define CONFIG_MCFUART |
6d0f6bcf | 25 | #define CONFIG_SYS_UART_PORT (0) |
8e585f02 | 26 | #define CONFIG_BAUDRATE 115200 |
8e585f02 TL |
27 | |
28 | #undef CONFIG_WATCHDOG | |
29 | #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ | |
30 | ||
ab77bc54 TL |
31 | /* Command line configuration */ |
32 | #include <config_cmd_default.h> | |
33 | ||
34 | #define CONFIG_CMD_CACHE | |
35 | #define CONFIG_CMD_DATE | |
36 | #define CONFIG_CMD_ELF | |
37 | #define CONFIG_CMD_FLASH | |
38 | #define CONFIG_CMD_I2C | |
39 | #define CONFIG_CMD_MEMORY | |
40 | #define CONFIG_CMD_MISC | |
41 | #define CONFIG_CMD_MII | |
42 | #define CONFIG_CMD_NET | |
43 | #define CONFIG_CMD_PING | |
44 | #define CONFIG_CMD_REGINFO | |
0dca874d | 45 | |
96d94385 | 46 | #ifdef CONFIG_NANDFLASH_SIZE |
ab77bc54 | 47 | # define CONFIG_CMD_NAND |
1a33ce65 TL |
48 | #endif |
49 | ||
6d0f6bcf | 50 | #define CONFIG_SYS_UNIFY_CACHE |
8e585f02 TL |
51 | |
52 | #define CONFIG_MCFFEC | |
53 | #ifdef CONFIG_MCFFEC | |
8e585f02 | 54 | # define CONFIG_MII 1 |
0f3ba7e9 | 55 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
56 | # define CONFIG_SYS_DISCOVER_PHY |
57 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
58 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8e585f02 | 59 | |
6d0f6bcf JCPV |
60 | # define CONFIG_SYS_FEC0_PINMUX 0 |
61 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 62 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
63 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
64 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
8e585f02 TL |
65 | # define FECDUPLEX FULL |
66 | # define FECSPEED _100BASET | |
67 | # else | |
6d0f6bcf JCPV |
68 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
69 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8e585f02 | 70 | # endif |
6d0f6bcf | 71 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
8e585f02 TL |
72 | #endif |
73 | ||
8e585f02 | 74 | #define CONFIG_MCFRTC |
48dbfeab | 75 | #undef RTC_DEBUG |
8e585f02 TL |
76 | |
77 | /* Timer */ | |
78 | #define CONFIG_MCFTMR | |
8e585f02 | 79 | #undef CONFIG_MCFPIT |
8e585f02 | 80 | |
eaf9e447 | 81 | /* I2C */ |
00f792e0 HS |
82 | #define CONFIG_SYS_I2C |
83 | #define CONFIG_SYS_I2C_FSL | |
84 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
85 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
86 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
6d0f6bcf | 87 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
eaf9e447 | 88 | |
8e585f02 | 89 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
ab77bc54 TL |
90 | #define CONFIG_UDP_CHECKSUM |
91 | ||
8e585f02 | 92 | #ifdef CONFIG_MCFFEC |
eaf9e447 TL |
93 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 |
94 | # define CONFIG_IPADDR 192.162.1.2 | |
95 | # define CONFIG_NETMASK 255.255.255.0 | |
96 | # define CONFIG_SERVERIP 192.162.1.1 | |
8e585f02 TL |
97 | # define CONFIG_GATEWAYIP 192.162.1.1 |
98 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
99 | #endif /* FEC_ENET */ | |
100 | ||
101 | #define CONFIG_HOSTNAME M5329EVB | |
102 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
103 | "netdev=eth0\0" \ | |
104 | "loadaddr=40010000\0" \ | |
105 | "u-boot=u-boot.bin\0" \ | |
106 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
107 | "upd=run load; run prog\0" \ | |
09933fb0 JJ |
108 | "prog=prot off 0 3ffff;" \ |
109 | "era 0 3ffff;" \ | |
8e585f02 TL |
110 | "cp.b ${loadaddr} 0 ${filesize};" \ |
111 | "save\0" \ | |
112 | "" | |
113 | ||
eaf9e447 | 114 | #define CONFIG_PRAM 512 /* 512 KB */ |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_PROMPT "-> " |
116 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
8e585f02 | 117 | |
ab77bc54 | 118 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 119 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8e585f02 | 120 | #else |
6d0f6bcf | 121 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8e585f02 TL |
122 | #endif |
123 | ||
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
125 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
126 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
127 | #define CONFIG_SYS_LOAD_ADDR 0x40010000 | |
8e585f02 | 128 | |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_CLK 80000000 |
130 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 | |
8e585f02 | 131 | |
6d0f6bcf | 132 | #define CONFIG_SYS_MBAR 0xFC000000 |
8e585f02 | 133 | |
6d0f6bcf | 134 | #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) |
1a33ce65 | 135 | |
8e585f02 TL |
136 | /* |
137 | * Low Level Configuration Settings | |
138 | * (address mappings, register initial values, etc.) | |
139 | * You should know what you are doing if you make changes here. | |
140 | */ | |
141 | /*----------------------------------------------------------------------- | |
142 | * Definitions for initial stack pointer and data area (in DPRAM) | |
143 | */ | |
6d0f6bcf | 144 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 145 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 146 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 147 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
6d0f6bcf | 148 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
8e585f02 TL |
149 | |
150 | /*----------------------------------------------------------------------- | |
151 | * Start addresses for the final memory configuration | |
152 | * (Set up by the startup code) | |
6d0f6bcf | 153 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
8e585f02 | 154 | */ |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
156 | #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ | |
157 | #define CONFIG_SYS_SDRAM_CFG1 0x53722730 | |
158 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
159 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 | |
160 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
161 | #define CONFIG_SYS_SDRAM_MODE 0x018D0000 | |
8e585f02 | 162 | |
6d0f6bcf JCPV |
163 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
164 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
8e585f02 | 165 | |
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
167 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
8e585f02 | 168 | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
170 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
8e585f02 TL |
171 | |
172 | /* | |
173 | * For booting Linux, the board info and command line data | |
174 | * have to be in the first 8 MB of memory, since this is | |
175 | * the maximum mapped by the Linux kernel during initialization ?? | |
176 | */ | |
6d0f6bcf | 177 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 178 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
8e585f02 TL |
179 | |
180 | /*----------------------------------------------------------------------- | |
181 | * FLASH organization | |
182 | */ | |
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_FLASH_CFI |
184 | #ifdef CONFIG_SYS_FLASH_CFI | |
00b1883a | 185 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
186 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
187 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
188 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
189 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
190 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
8e585f02 TL |
191 | #endif |
192 | ||
96d94385 | 193 | #ifdef CONFIG_NANDFLASH_SIZE |
6d0f6bcf JCPV |
194 | # define CONFIG_SYS_MAX_NAND_DEVICE 1 |
195 | # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE | |
196 | # define CONFIG_SYS_NAND_SIZE 1 | |
197 | # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
ab77bc54 TL |
198 | # define NAND_ALLOW_ERASE_ALL 1 |
199 | # define CONFIG_JFFS2_NAND 1 | |
200 | # define CONFIG_JFFS2_DEV "nand0" | |
6d0f6bcf | 201 | # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) |
ab77bc54 | 202 | # define CONFIG_JFFS2_PART_OFFSET 0x00000000 |
1a33ce65 TL |
203 | #endif |
204 | ||
6d0f6bcf | 205 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
8e585f02 TL |
206 | |
207 | /* Configuration for environment | |
208 | * Environment is embedded in u-boot in the second sector of the flash | |
209 | */ | |
0e8d1586 JCPV |
210 | #define CONFIG_ENV_OFFSET 0x4000 |
211 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 212 | #define CONFIG_ENV_IS_IN_FLASH 1 |
8e585f02 TL |
213 | |
214 | /*----------------------------------------------------------------------- | |
215 | * Cache Configuration | |
216 | */ | |
6d0f6bcf | 217 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
8e585f02 | 218 | |
dd9f054e | 219 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 220 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 221 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 222 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
223 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
224 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
225 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
226 | CF_ACR_EN | CF_ACR_SM_ALL) | |
227 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ | |
228 | CF_CACR_DCM_P) | |
229 | ||
8e585f02 TL |
230 | /*----------------------------------------------------------------------- |
231 | * Chipselect bank definitions | |
232 | */ | |
233 | /* | |
234 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
235 | * CS1 - CompactFlash and registers | |
236 | * CS2 - NAND Flash 16, 32, or 64MB | |
237 | * CS3 - Available | |
238 | * CS4 - Available | |
239 | * CS5 - Available | |
240 | */ | |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_CS0_BASE 0 |
242 | #define CONFIG_SYS_CS0_MASK 0x007f0001 | |
243 | #define CONFIG_SYS_CS0_CTRL 0x00001fa0 | |
8e585f02 | 244 | |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_CS1_BASE 0x10000000 |
246 | #define CONFIG_SYS_CS1_MASK 0x001f0001 | |
247 | #define CONFIG_SYS_CS1_CTRL 0x002A3780 | |
8e585f02 | 248 | |
96d94385 | 249 | #ifdef CONFIG_NANDFLASH_SIZE |
6d0f6bcf | 250 | #define CONFIG_SYS_CS2_BASE 0x20000000 |
96d94385 | 251 | #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) |
6d0f6bcf | 252 | #define CONFIG_SYS_CS2_CTRL 0x00001f60 |
8e585f02 TL |
253 | #endif |
254 | ||
8e585f02 | 255 | #endif /* _M5329EVB_H */ |