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8e585f02 TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF5329 FireEngine board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
8e585f02 TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M5329EVB_H | |
15 | #define _M5329EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
8e585f02 | 21 | |
9998bd37 | 22 | #define CONFIG_MCFUART |
6d0f6bcf | 23 | #define CONFIG_SYS_UART_PORT (0) |
8e585f02 | 24 | #define CONFIG_BAUDRATE 115200 |
8e585f02 TL |
25 | |
26 | #undef CONFIG_WATCHDOG | |
27 | #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ | |
28 | ||
ab77bc54 | 29 | /* Command line configuration */ |
ab77bc54 TL |
30 | #define CONFIG_CMD_CACHE |
31 | #define CONFIG_CMD_DATE | |
32 | #define CONFIG_CMD_ELF | |
ab77bc54 | 33 | #define CONFIG_CMD_I2C |
ab77bc54 | 34 | #define CONFIG_CMD_MII |
ab77bc54 TL |
35 | #define CONFIG_CMD_PING |
36 | #define CONFIG_CMD_REGINFO | |
0dca874d | 37 | |
96d94385 | 38 | #ifdef CONFIG_NANDFLASH_SIZE |
ab77bc54 | 39 | # define CONFIG_CMD_NAND |
1a33ce65 TL |
40 | #endif |
41 | ||
6d0f6bcf | 42 | #define CONFIG_SYS_UNIFY_CACHE |
8e585f02 TL |
43 | |
44 | #define CONFIG_MCFFEC | |
45 | #ifdef CONFIG_MCFFEC | |
8e585f02 | 46 | # define CONFIG_MII 1 |
0f3ba7e9 | 47 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
48 | # define CONFIG_SYS_DISCOVER_PHY |
49 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
50 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8e585f02 | 51 | |
6d0f6bcf JCPV |
52 | # define CONFIG_SYS_FEC0_PINMUX 0 |
53 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 54 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
55 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
56 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
8e585f02 TL |
57 | # define FECDUPLEX FULL |
58 | # define FECSPEED _100BASET | |
59 | # else | |
6d0f6bcf JCPV |
60 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
61 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8e585f02 | 62 | # endif |
6d0f6bcf | 63 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
8e585f02 TL |
64 | #endif |
65 | ||
8e585f02 | 66 | #define CONFIG_MCFRTC |
48dbfeab | 67 | #undef RTC_DEBUG |
8e585f02 TL |
68 | |
69 | /* Timer */ | |
70 | #define CONFIG_MCFTMR | |
8e585f02 | 71 | #undef CONFIG_MCFPIT |
8e585f02 | 72 | |
eaf9e447 | 73 | /* I2C */ |
00f792e0 HS |
74 | #define CONFIG_SYS_I2C |
75 | #define CONFIG_SYS_I2C_FSL | |
76 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
77 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
78 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
6d0f6bcf | 79 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
eaf9e447 | 80 | |
8e585f02 | 81 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
ab77bc54 TL |
82 | #define CONFIG_UDP_CHECKSUM |
83 | ||
8e585f02 | 84 | #ifdef CONFIG_MCFFEC |
eaf9e447 TL |
85 | # define CONFIG_IPADDR 192.162.1.2 |
86 | # define CONFIG_NETMASK 255.255.255.0 | |
87 | # define CONFIG_SERVERIP 192.162.1.1 | |
8e585f02 | 88 | # define CONFIG_GATEWAYIP 192.162.1.1 |
8e585f02 TL |
89 | #endif /* FEC_ENET */ |
90 | ||
91 | #define CONFIG_HOSTNAME M5329EVB | |
92 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
93 | "netdev=eth0\0" \ | |
94 | "loadaddr=40010000\0" \ | |
95 | "u-boot=u-boot.bin\0" \ | |
96 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
97 | "upd=run load; run prog\0" \ | |
09933fb0 JJ |
98 | "prog=prot off 0 3ffff;" \ |
99 | "era 0 3ffff;" \ | |
8e585f02 TL |
100 | "cp.b ${loadaddr} 0 ${filesize};" \ |
101 | "save\0" \ | |
102 | "" | |
103 | ||
eaf9e447 | 104 | #define CONFIG_PRAM 512 /* 512 KB */ |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_PROMPT "-> " |
106 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
8e585f02 | 107 | |
ab77bc54 | 108 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 109 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8e585f02 | 110 | #else |
6d0f6bcf | 111 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8e585f02 TL |
112 | #endif |
113 | ||
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
115 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
116 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
117 | #define CONFIG_SYS_LOAD_ADDR 0x40010000 | |
8e585f02 | 118 | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_CLK 80000000 |
120 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 | |
8e585f02 | 121 | |
6d0f6bcf | 122 | #define CONFIG_SYS_MBAR 0xFC000000 |
8e585f02 | 123 | |
6d0f6bcf | 124 | #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) |
1a33ce65 | 125 | |
8e585f02 TL |
126 | /* |
127 | * Low Level Configuration Settings | |
128 | * (address mappings, register initial values, etc.) | |
129 | * You should know what you are doing if you make changes here. | |
130 | */ | |
131 | /*----------------------------------------------------------------------- | |
132 | * Definitions for initial stack pointer and data area (in DPRAM) | |
133 | */ | |
6d0f6bcf | 134 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 135 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 136 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 137 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
6d0f6bcf | 138 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
8e585f02 TL |
139 | |
140 | /*----------------------------------------------------------------------- | |
141 | * Start addresses for the final memory configuration | |
142 | * (Set up by the startup code) | |
6d0f6bcf | 143 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
8e585f02 | 144 | */ |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
146 | #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ | |
147 | #define CONFIG_SYS_SDRAM_CFG1 0x53722730 | |
148 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
149 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 | |
150 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
151 | #define CONFIG_SYS_SDRAM_MODE 0x018D0000 | |
8e585f02 | 152 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
154 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
8e585f02 | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
157 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
8e585f02 | 158 | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
160 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
8e585f02 TL |
161 | |
162 | /* | |
163 | * For booting Linux, the board info and command line data | |
164 | * have to be in the first 8 MB of memory, since this is | |
165 | * the maximum mapped by the Linux kernel during initialization ?? | |
166 | */ | |
6d0f6bcf | 167 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 168 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
8e585f02 TL |
169 | |
170 | /*----------------------------------------------------------------------- | |
171 | * FLASH organization | |
172 | */ | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_FLASH_CFI |
174 | #ifdef CONFIG_SYS_FLASH_CFI | |
00b1883a | 175 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
176 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
177 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
178 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
179 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
180 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
8e585f02 TL |
181 | #endif |
182 | ||
96d94385 | 183 | #ifdef CONFIG_NANDFLASH_SIZE |
6d0f6bcf JCPV |
184 | # define CONFIG_SYS_MAX_NAND_DEVICE 1 |
185 | # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE | |
186 | # define CONFIG_SYS_NAND_SIZE 1 | |
187 | # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
ab77bc54 TL |
188 | # define NAND_ALLOW_ERASE_ALL 1 |
189 | # define CONFIG_JFFS2_NAND 1 | |
190 | # define CONFIG_JFFS2_DEV "nand0" | |
6d0f6bcf | 191 | # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) |
ab77bc54 | 192 | # define CONFIG_JFFS2_PART_OFFSET 0x00000000 |
1a33ce65 TL |
193 | #endif |
194 | ||
6d0f6bcf | 195 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
8e585f02 TL |
196 | |
197 | /* Configuration for environment | |
198 | * Environment is embedded in u-boot in the second sector of the flash | |
199 | */ | |
0e8d1586 JCPV |
200 | #define CONFIG_ENV_OFFSET 0x4000 |
201 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 202 | #define CONFIG_ENV_IS_IN_FLASH 1 |
8e585f02 | 203 | |
5296cb1d | 204 | #define LDS_BOARD_TEXT \ |
205 | . = DEFINED(env_offset) ? env_offset : .; \ | |
206 | common/env_embedded.o (.text*); | |
207 | ||
8e585f02 TL |
208 | /*----------------------------------------------------------------------- |
209 | * Cache Configuration | |
210 | */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
8e585f02 | 212 | |
dd9f054e | 213 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 214 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 215 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 216 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
217 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
218 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
219 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
220 | CF_ACR_EN | CF_ACR_SM_ALL) | |
221 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ | |
222 | CF_CACR_DCM_P) | |
223 | ||
8e585f02 TL |
224 | /*----------------------------------------------------------------------- |
225 | * Chipselect bank definitions | |
226 | */ | |
227 | /* | |
228 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
229 | * CS1 - CompactFlash and registers | |
230 | * CS2 - NAND Flash 16, 32, or 64MB | |
231 | * CS3 - Available | |
232 | * CS4 - Available | |
233 | * CS5 - Available | |
234 | */ | |
6d0f6bcf JCPV |
235 | #define CONFIG_SYS_CS0_BASE 0 |
236 | #define CONFIG_SYS_CS0_MASK 0x007f0001 | |
237 | #define CONFIG_SYS_CS0_CTRL 0x00001fa0 | |
8e585f02 | 238 | |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_CS1_BASE 0x10000000 |
240 | #define CONFIG_SYS_CS1_MASK 0x001f0001 | |
241 | #define CONFIG_SYS_CS1_CTRL 0x002A3780 | |
8e585f02 | 242 | |
96d94385 | 243 | #ifdef CONFIG_NANDFLASH_SIZE |
6d0f6bcf | 244 | #define CONFIG_SYS_CS2_BASE 0x20000000 |
96d94385 | 245 | #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) |
6d0f6bcf | 246 | #define CONFIG_SYS_CS2_CTRL 0x00001f60 |
8e585f02 TL |
247 | #endif |
248 | ||
8e585f02 | 249 | #endif /* _M5329EVB_H */ |