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186fc4db AW |
1 | /* |
2 | * Configuation settings for the Freescale MCF54418 TWR board. | |
3 | * | |
4 | * Copyright 2010-2012 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
186fc4db AW |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M54418TWR_H | |
15 | #define _M54418TWR_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
186fc4db AW |
21 | #define CONFIG_M54418TWR /* M54418TWR board */ |
22 | ||
23 | #define CONFIG_MCFUART | |
24 | #define CONFIG_SYS_UART_PORT (0) | |
25 | #define CONFIG_BAUDRATE 115200 | |
26 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } | |
27 | ||
28 | #undef CONFIG_WATCHDOG | |
29 | ||
30 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
31 | ||
32 | /* | |
33 | * BOOTP options | |
34 | */ | |
35 | #define CONFIG_BOOTP_BOOTFILESIZE | |
36 | #define CONFIG_BOOTP_BOOTPATH | |
37 | #define CONFIG_BOOTP_GATEWAY | |
38 | #define CONFIG_BOOTP_HOSTNAME | |
39 | ||
40 | /* Command line configuration */ | |
186fc4db AW |
41 | #define CONFIG_CMD_CACHE |
42 | #undef CONFIG_CMD_DATE | |
43 | #define CONFIG_CMD_DHCP | |
44 | #define CONFIG_CMD_ELF | |
186fc4db AW |
45 | #undef CONFIG_CMD_I2C |
46 | #undef CONFIG_CMD_JFFS2 | |
47 | #undef CONFIG_CMD_UBI | |
186fc4db AW |
48 | #define CONFIG_CMD_MII |
49 | #undef CONFIG_CMD_NAND | |
186fc4db AW |
50 | #define CONFIG_CMD_PING |
51 | #define CONFIG_CMD_REGINFO | |
52 | #define CONFIG_CMD_SPI | |
53 | #define CONFIG_CMD_SF | |
186fc4db | 54 | |
186fc4db AW |
55 | |
56 | /* | |
57 | * NAND FLASH | |
58 | */ | |
59 | #ifdef CONFIG_CMD_NAND | |
60 | #define CONFIG_JFFS2_NAND | |
61 | #define CONFIG_NAND_FSL_NFC | |
62 | #define CONFIG_SYS_NAND_BASE 0xFC0FC000 | |
63 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
64 | #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
65 | #define CONFIG_SYS_NAND_SELECT_DEVICE | |
186fc4db AW |
66 | #endif |
67 | ||
68 | /* Network configuration */ | |
69 | #define CONFIG_MCFFEC | |
70 | #ifdef CONFIG_MCFFEC | |
186fc4db AW |
71 | #define CONFIG_MII 1 |
72 | #define CONFIG_MII_INIT 1 | |
73 | #define CONFIG_SYS_DISCOVER_PHY | |
74 | #define CONFIG_SYS_RX_ETH_BUFFER 2 | |
75 | #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN | |
76 | #define CONFIG_SYS_TX_ETH_BUFFER 2 | |
77 | #define CONFIG_HAS_ETH1 | |
78 | ||
79 | #define CONFIG_SYS_FEC0_PINMUX 0 | |
80 | #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
81 | #define CONFIG_SYS_FEC1_PINMUX 0 | |
82 | #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE | |
83 | #define MCFFEC_TOUT_LOOP 50000 | |
84 | #define CONFIG_SYS_FEC0_PHYADDR 0 | |
85 | #define CONFIG_SYS_FEC1_PHYADDR 1 | |
86 | ||
87 | #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ | |
88 | ||
89 | #ifdef CONFIG_SYS_NAND_BOOT | |
90 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ | |
91 | "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ | |
92 | "-(jffs2) console=ttyS0,115200" | |
93 | #else | |
94 | #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ | |
95 | __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ | |
96 | __stringify(CONFIG_IPADDR) " ip=" \ | |
97 | __stringify(CONFIG_IPADDR) ":" \ | |
98 | __stringify(CONFIG_SERVERIP)":" \ | |
99 | __stringify(CONFIG_GATEWAYIP)": " \ | |
100 | __stringify(CONFIG_NETMASK) \ | |
101 | "::eth0:off:rw console=ttyS0,115200" | |
102 | #endif | |
103 | ||
186fc4db AW |
104 | #define CONFIG_ETHPRIME "FEC0" |
105 | #define CONFIG_IPADDR 192.168.1.2 | |
106 | #define CONFIG_NETMASK 255.255.255.0 | |
107 | #define CONFIG_SERVERIP 192.168.1.1 | |
108 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
109 | ||
186fc4db AW |
110 | #define CONFIG_SYS_FEC_BUF_USE_SRAM |
111 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ | |
112 | #ifndef CONFIG_SYS_DISCOVER_PHY | |
113 | #define FECDUPLEX FULL | |
114 | #define FECSPEED _100BASET | |
115 | #define LINKSTATUS 1 | |
116 | #else | |
117 | #define LINKSTATUS 0 | |
118 | #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
119 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
120 | #endif | |
121 | #endif /* CONFIG_SYS_DISCOVER_PHY */ | |
122 | #endif | |
123 | ||
124 | #define CONFIG_HOSTNAME M54418TWR | |
125 | ||
126 | #if defined(CONFIG_CF_SBF) | |
127 | /* ST Micro serial flash */ | |
128 | #define CONFIG_SYS_LOAD_ADDR2 0x40010007 | |
129 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
130 | "netdev=eth0\0" \ | |
131 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ | |
132 | "loadaddr=0x40010000\0" \ | |
133 | "sbfhdr=sbfhdr.bin\0" \ | |
134 | "uboot=u-boot.bin\0" \ | |
135 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
136 | "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ | |
137 | "upd=run load; run prog\0" \ | |
138 | "prog=sf probe 0:1 1000000 3;" \ | |
139 | "sf erase 0 40000;" \ | |
140 | "sf write ${loadaddr} 0 40000;" \ | |
141 | "save\0" \ | |
142 | "" | |
143 | #elif defined(CONFIG_SYS_NAND_BOOT) | |
144 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
145 | "netdev=eth0\0" \ | |
146 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ | |
147 | "loadaddr=0x40010000\0" \ | |
148 | "u-boot=u-boot.bin\0" \ | |
149 | "load=tftp ${loadaddr} ${u-boot};\0" \ | |
150 | "upd=run load; run prog\0" \ | |
151 | "prog=nand device 0;" \ | |
152 | "nand erase 0 40000;" \ | |
153 | "nb_update ${loadaddr} ${filesize};" \ | |
154 | "save\0" \ | |
155 | "" | |
156 | #else | |
157 | #define CONFIG_SYS_UBOOT_END 0x3FFFF | |
158 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
159 | "netdev=eth0\0" \ | |
160 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ | |
161 | "loadaddr=40010000\0" \ | |
162 | "u-boot=u-boot.bin\0" \ | |
163 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
164 | "upd=run load; run prog\0" \ | |
165 | "prog=prot off mram" " ;" \ | |
166 | "cp.b ${loadaddr} 0 ${filesize};" \ | |
167 | "save\0" \ | |
168 | "" | |
169 | #endif | |
170 | ||
171 | /* Realtime clock */ | |
172 | #undef CONFIG_MCFRTC | |
173 | #define CONFIG_RTC_MCFRRTC | |
174 | #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 | |
175 | ||
176 | /* Timer */ | |
177 | #define CONFIG_MCFTMR | |
178 | #undef CONFIG_MCFPIT | |
179 | ||
180 | /* I2c */ | |
00f792e0 | 181 | #undef CONFIG_SYS_FSL_I2C |
186fc4db | 182 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ |
ea818dbb | 183 | #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
186fc4db AW |
184 | /* I2C speed and slave address */ |
185 | #define CONFIG_SYS_I2C_SPEED 80000 | |
186 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
187 | #define CONFIG_SYS_I2C_OFFSET 0x58000 | |
188 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR | |
189 | ||
190 | /* DSPI and Serial Flash */ | |
191 | #define CONFIG_CF_SPI | |
192 | #define CONFIG_CF_DSPI | |
193 | #define CONFIG_SERIAL_FLASH | |
194 | #define CONFIG_HARD_SPI | |
195 | #define CONFIG_SYS_SBFHDR_SIZE 0x7 | |
196 | #ifdef CONFIG_CMD_SPI | |
186fc4db AW |
197 | # define CONFIG_SPI_FLASH_ATMEL |
198 | ||
199 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ | |
200 | DSPI_CTAR_PCSSCK_1CLK | \ | |
201 | DSPI_CTAR_PASC(0) | \ | |
202 | DSPI_CTAR_PDT(0) | \ | |
203 | DSPI_CTAR_CSSCK(0) | \ | |
204 | DSPI_CTAR_ASC(0) | \ | |
205 | DSPI_CTAR_DT(1)) | |
206 | # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) | |
207 | # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) | |
208 | #endif | |
209 | ||
210 | /* Input, PCI, Flexbus, and VCO */ | |
211 | #define CONFIG_EXTRA_CLOCK | |
212 | ||
213 | #define CONFIG_PRAM 2048 /* 2048 KB */ | |
214 | ||
215 | /* HUSH */ | |
216 | #define CONFIG_SYS_HUSH_PARSER 1 | |
217 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
218 | ||
186fc4db AW |
219 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
220 | ||
221 | #if defined(CONFIG_CMD_KGDB) | |
222 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
223 | #else | |
224 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
225 | #endif | |
226 | /* Print Buffer Size */ | |
227 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
228 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
229 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
230 | /* Boot Argument Buffer Size */ | |
231 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
232 | ||
233 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) | |
234 | ||
186fc4db AW |
235 | #define CONFIG_SYS_MBAR 0xFC000000 |
236 | ||
237 | /* | |
238 | * Low Level Configuration Settings | |
239 | * (address mappings, register initial values, etc.) | |
240 | * You should know what you are doing if you make changes here. | |
241 | */ | |
242 | ||
243 | /*----------------------------------------------------------------------- | |
244 | * Definitions for initial stack pointer and data area (in DPRAM) | |
245 | */ | |
246 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 | |
247 | /* End of used area in internal SRAM */ | |
248 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 | |
249 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 | |
186fc4db | 250 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ |
627b73e2 | 251 | GENERATED_GBL_DATA_SIZE) - 32) |
186fc4db AW |
252 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
253 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) | |
254 | ||
255 | /*----------------------------------------------------------------------- | |
256 | * Start addresses for the final memory configuration | |
257 | * (Set up by the startup code) | |
258 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
259 | */ | |
260 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
261 | #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ | |
262 | ||
263 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) | |
264 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
265 | #define CONFIG_SYS_DRAM_TEST | |
266 | ||
267 | #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) | |
268 | #define CONFIG_SERIAL_BOOT | |
269 | #endif | |
270 | ||
271 | #if defined(CONFIG_SERIAL_BOOT) | |
272 | #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) | |
273 | #else | |
274 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
275 | #endif | |
276 | ||
277 | #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) | |
278 | /* Reserve 256 kB for Monitor */ | |
279 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
280 | /* Reserve 256 kB for malloc() */ | |
281 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
282 | ||
283 | /* | |
284 | * For booting Linux, the board info and command line data | |
285 | * have to be in the first 8 MB of memory, since this is | |
286 | * the maximum mapped by the Linux kernel during initialization ?? | |
287 | */ | |
288 | /* Initial Memory map for Linux */ | |
289 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ | |
290 | (CONFIG_SYS_SDRAM_SIZE << 20)) | |
291 | ||
292 | /* Configuration for environment | |
293 | * Environment is embedded in u-boot in the second sector of the flash | |
294 | */ | |
295 | #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ | |
296 | #define CONFIG_SYS_NO_FLASH | |
297 | #define CONFIG_ENV_IS_IN_MRAM 1 | |
298 | #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ | |
299 | #define CONFIG_ENV_SIZE 0x1000 | |
300 | #endif | |
301 | ||
302 | #if defined(CONFIG_CF_SBF) | |
303 | #define CONFIG_SYS_NO_FLASH | |
304 | #define CONFIG_ENV_IS_IN_SPI_FLASH 1 | |
305 | #define CONFIG_ENV_SPI_CS 1 | |
306 | #define CONFIG_ENV_OFFSET 0x40000 | |
307 | #define CONFIG_ENV_SIZE 0x2000 | |
308 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
309 | #endif | |
310 | #if defined(CONFIG_SYS_NAND_BOOT) | |
311 | #define CONFIG_SYS_NO_FLASH | |
b765fce9 | 312 | #define CONFIG_ENV_IS_NOWHERE |
186fc4db AW |
313 | #define CONFIG_ENV_OFFSET 0x80000 |
314 | #define CONFIG_ENV_SIZE 0x20000 | |
315 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
316 | #endif | |
317 | #undef CONFIG_ENV_OVERWRITE | |
318 | ||
319 | /* FLASH organization */ | |
320 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
321 | ||
322 | #undef CONFIG_SYS_FLASH_CFI | |
323 | #ifdef CONFIG_SYS_FLASH_CFI | |
324 | ||
325 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
326 | /* Max size that the board might have */ | |
327 | #define CONFIG_SYS_FLASH_SIZE 0x1000000 | |
328 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
329 | /* max number of memory banks */ | |
330 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
331 | /* max number of sectors on one chip */ | |
332 | #define CONFIG_SYS_MAX_FLASH_SECT 270 | |
333 | /* "Real" (hardware) sectors protection */ | |
334 | #define CONFIG_SYS_FLASH_PROTECTION | |
335 | #define CONFIG_SYS_FLASH_CHECKSUM | |
336 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } | |
337 | #else | |
338 | /* max number of sectors on one chip */ | |
339 | #define CONFIG_SYS_MAX_FLASH_SECT 270 | |
340 | /* max number of sectors on one chip */ | |
341 | #define CONFIG_SYS_MAX_FLASH_BANKS 0 | |
342 | #endif | |
343 | ||
344 | /* | |
345 | * This is setting for JFFS2 support in u-boot. | |
346 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
347 | */ | |
348 | #ifdef CONFIG_CMD_JFFS2 | |
349 | #define CONFIG_JFFS2_DEV "nand0" | |
350 | #define CONFIG_JFFS2_PART_OFFSET (0x800000) | |
351 | #define CONFIG_CMD_MTDPARTS | |
352 | #define CONFIG_MTD_DEVICE | |
353 | #define MTDIDS_DEFAULT "nand0=m54418twr.nand" | |
354 | ||
355 | #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ | |
356 | "7m(kernel)," \ | |
357 | "-(rootfs)" | |
358 | ||
359 | #endif | |
360 | ||
361 | #ifdef CONFIG_CMD_UBI | |
362 | #define CONFIG_CMD_MTDPARTS | |
363 | #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ | |
364 | #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ | |
365 | #define CONFIG_RBTREE | |
366 | #define MTDIDS_DEFAULT "nand0=NAND" | |
367 | #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ | |
368 | "-(ubi)" | |
369 | #endif | |
370 | /* Cache Configuration */ | |
371 | #define CONFIG_SYS_CACHELINE_SIZE 16 | |
372 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
373 | CONFIG_SYS_INIT_RAM_SIZE - 8) | |
374 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
375 | CONFIG_SYS_INIT_RAM_SIZE - 4) | |
376 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) | |
377 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
378 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
379 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
380 | CF_ACR_EN | CF_ACR_SM_ALL) | |
381 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ | |
382 | CF_CACR_ICINVA | CF_CACR_EUSP) | |
383 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
384 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
385 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
386 | ||
387 | #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
388 | CONFIG_SYS_INIT_RAM_SIZE - 12) | |
389 | ||
390 | /*----------------------------------------------------------------------- | |
391 | * Memory bank definitions | |
392 | */ | |
393 | /* | |
394 | * CS0 - NOR Flash 16MB | |
395 | * CS1 - Available | |
396 | * CS2 - Available | |
397 | * CS3 - Available | |
398 | * CS4 - Available | |
399 | * CS5 - Available | |
400 | */ | |
401 | ||
402 | /* Flash */ | |
403 | #define CONFIG_SYS_CS0_BASE 0x00000000 | |
404 | #define CONFIG_SYS_CS0_MASK 0x000F0101 | |
405 | #define CONFIG_SYS_CS0_CTRL 0x00001D60 | |
406 | ||
407 | #endif /* _M54418TWR_H */ |