[thirdparty/u-boot.git] / include / configs / M54418TWR.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for the Freescale MCF54418 TWR board.
 *
 * Copyright 2010-2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54418TWR_H
#define _M54418TWR_H

#include <linux/stringify.h>

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

#define LDS_BOARD_TEXT			board/freescale/m54418twr/sbf_dram_init.o (.text*)

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * NAND FLASH
 */
#ifdef CONFIG_CMD_NAND
#define CONFIG_JFFS2_NAND
#define CONFIG_NAND_FSL_NFC
#define CONFIG_SYS_NAND_BASE		0xFC0FC000
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS			CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_SELECT_DEVICE
#endif

/* Network configuration */
#ifdef CONFIG_MCFFEC
#define CONFIG_MII_INIT		1
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_RX_ETH_BUFFER	2
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#define CONFIG_SYS_TX_ETH_BUFFER	2
#define CONFIG_HAS_ETH1

#define CONFIG_ETHPRIME	"FEC0"
#define CONFIG_IPADDR		192.168.1.2
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_SERVERIP	192.168.1.1
#define CONFIG_GATEWAYIP	192.168.1.1

#define CONFIG_SYS_FEC_BUF_USE_SRAM
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#ifndef CONFIG_SYS_DISCOVER_PHY
#define FECDUPLEX	FULL
#define FECSPEED	_100BASET
#define LINKSTATUS	1
#else
#define LINKSTATUS	0
#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#endif
#endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		"M54418TWR"

#if defined(CONFIG_CF_SBF)
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 1000000 3;"		\
	"sf erase 0 40000;"			\
	"sf write ${loadaddr} 0 40000;"		\
	"save\0"				\
	""
#elif defined(CONFIG_SYS_NAND_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${u-boot};\0"	\
	"upd=run load; run prog\0"		\
	"prog=nand device 0;"			\
	"nand erase 0 40000;"			\
	"nb_update ${loadaddr} ${filesize};"	\
	"save\0"				\
	""
#else
#define CONFIG_SYS_UBOOT_END	0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off mram" " ;"	\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""
#endif

/* Realtime clock */
#undef CONFIG_MCFRTC
#define CONFIG_RTC_MCFRRTC
#define CONFIG_SYS_MCFRRTC_BASE		0xFC0A8000

/* Timer */
#define CONFIG_MCFTMR

/* I2c */
#undef CONFIG_SYS_FSL_I2C
#undef	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged */
/* I2C speed and slave address  */
#define CONFIG_SYS_I2C_SPEED		80000
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x58000
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_SYS_SBFHDR_SIZE		0x7

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM			2048	/* 2048 KB */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
/* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */

#define CONFIG_SYS_DRAM_TEST

#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
#define CONFIG_SERIAL_BOOT
#endif

#if defined(CONFIG_SERIAL_BOOT)
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
				(CONFIG_SYS_SDRAM_SIZE << 20))

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */

#undef CONFIG_ENV_OVERWRITE

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

#ifdef CONFIG_SYS_FLASH_CFI

/* Max size that the board might have */
#define CONFIG_SYS_FLASH_SIZE		0x1000000
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT	270
/* "Real" (hardware) sectors protection */
#define CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
#else
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT	270
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	0
#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_DEV		"nand0"
#define CONFIG_JFFS2_PART_OFFSET	(0x800000)

#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16
#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
					 CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR + \
			CONFIG_SYS_INIT_RAM_SIZE - 12)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 16MB
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

 /* Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x000F0101
#define CONFIG_SYS_CS0_CTRL		0x00001D60

#endif				/* _M54418TWR_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
186fc4db AW	2	/*
	3	* Configuation settings for the Freescale MCF54418 TWR board.
	4	*
	5	* Copyright 2010-2012 Freescale Semiconductor, Inc.
	6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
186fc4db AW	7	*/
	8
	9	/*
	10	* board/config.h - configuration options, board specific
	11	*/
	12
	13	#ifndef _M54418TWR_H
	14	#define _M54418TWR_H
	15
1af3c7f4 SG	16	#include <linux/stringify.h>
1af3c7f4 SG	17
186fc4db AW	18	/*
	19	* High Level Configuration Options
	20	* (easy to change)
	21	*/
186fc4db AW	22
	23	#define CONFIG_MCFUART
	24	#define CONFIG_SYS_UART_PORT (0)
186fc4db AW	25	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
186fc4db AW	26
c74dda8b AD	27	#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
c74dda8b AD	28
186fc4db AW	29	#undef CONFIG_WATCHDOG
	30
	31	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	32
	33	/*
	34	* BOOTP options
	35	*/
	36	#define CONFIG_BOOTP_BOOTFILESIZE
186fc4db	37
186fc4db AW	38	/*
	39	* NAND FLASH
	40	*/
	41	#ifdef CONFIG_CMD_NAND
	42	#define CONFIG_JFFS2_NAND
	43	#define CONFIG_NAND_FSL_NFC
	44	#define CONFIG_SYS_NAND_BASE 0xFC0FC000
	45	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	46	#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
	47	#define CONFIG_SYS_NAND_SELECT_DEVICE
186fc4db AW	48	#endif
	49
	50	/* Network configuration */
186fc4db	51	#ifdef CONFIG_MCFFEC
186fc4db AW	52	#define CONFIG_MII_INIT 1
	53	#define CONFIG_SYS_DISCOVER_PHY
	54	#define CONFIG_SYS_RX_ETH_BUFFER 2
e34b913a	55	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
186fc4db AW	56	#define CONFIG_SYS_TX_ETH_BUFFER 2
	57	#define CONFIG_HAS_ETH1
	58
186fc4db AW	59	#define CONFIG_ETHPRIME "FEC0"
	60	#define CONFIG_IPADDR 192.168.1.2
	61	#define CONFIG_NETMASK 255.255.255.0
	62	#define CONFIG_SERVERIP 192.168.1.1
	63	#define CONFIG_GATEWAYIP 192.168.1.1
	64
186fc4db AW	65	#define CONFIG_SYS_FEC_BUF_USE_SRAM
	66	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
	67	#ifndef CONFIG_SYS_DISCOVER_PHY
	68	#define FECDUPLEX FULL
	69	#define FECSPEED _100BASET
	70	#define LINKSTATUS 1
	71	#else
	72	#define LINKSTATUS 0
	73	#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	74	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	75	#endif
	76	#endif /* CONFIG_SYS_DISCOVER_PHY */
	77	#endif
	78
5bc0543d	79	#define CONFIG_HOSTNAME "M54418TWR"
186fc4db AW	80
	81	#if defined(CONFIG_CF_SBF)
	82	/* ST Micro serial flash */
	83	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
	84	#define CONFIG_EXTRA_ENV_SETTINGS \
	85	"netdev=eth0\0" \
	86	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
	87	"loadaddr=0x40010000\0" \
	88	"sbfhdr=sbfhdr.bin\0" \
	89	"uboot=u-boot.bin\0" \
	90	"load=tftp ${loadaddr} ${sbfhdr};" \
	91	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
	92	"upd=run load; run prog\0" \
	93	"prog=sf probe 0:1 1000000 3;" \
	94	"sf erase 0 40000;" \
	95	"sf write ${loadaddr} 0 40000;" \
	96	"save\0" \
	97	""
	98	#elif defined(CONFIG_SYS_NAND_BOOT)
	99	#define CONFIG_EXTRA_ENV_SETTINGS \
	100	"netdev=eth0\0" \
	101	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
	102	"loadaddr=0x40010000\0" \
	103	"u-boot=u-boot.bin\0" \
	104	"load=tftp ${loadaddr} ${u-boot};\0" \
	105	"upd=run load; run prog\0" \
	106	"prog=nand device 0;" \
	107	"nand erase 0 40000;" \
	108	"nb_update ${loadaddr} ${filesize};" \
	109	"save\0" \
	110	""
	111	#else
	112	#define CONFIG_SYS_UBOOT_END 0x3FFFF
	113	#define CONFIG_EXTRA_ENV_SETTINGS \
	114	"netdev=eth0\0" \
	115	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
	116	"loadaddr=40010000\0" \
	117	"u-boot=u-boot.bin\0" \
	118	"load=tftp ${loadaddr) ${u-boot}\0" \
	119	"upd=run load; run prog\0" \
	120	"prog=prot off mram" " ;" \
	121	"cp.b ${loadaddr} 0 ${filesize};" \
	122	"save\0" \
	123	""
	124	#endif
	125
	126	/* Realtime clock */
	127	#undef CONFIG_MCFRTC
	128	#define CONFIG_RTC_MCFRRTC
	129	#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
	130
	131	/* Timer */
	132	#define CONFIG_MCFTMR
186fc4db AW	133
186fc4db AW	134	/* I2c */
00f792e0	135	#undef CONFIG_SYS_FSL_I2C
ea818dbb	136	#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
186fc4db AW	137	/* I2C speed and slave address */
	138	#define CONFIG_SYS_I2C_SPEED 80000
	139	#define CONFIG_SYS_I2C_SLAVE 0x7F
	140	#define CONFIG_SYS_I2C_OFFSET 0x58000
	141	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	142
	143	/* DSPI and Serial Flash */
186fc4db AW	144	#define CONFIG_CF_DSPI
186fc4db AW	145	#define CONFIG_SERIAL_FLASH
186fc4db	146	#define CONFIG_SYS_SBFHDR_SIZE 0x7
186fc4db AW	147
	148	/* Input, PCI, Flexbus, and VCO */
	149	#define CONFIG_EXTRA_CLOCK
	150
	151	#define CONFIG_PRAM 2048 /* 2048 KB */
	152
186fc4db AW	153	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
186fc4db AW	154
186fc4db AW	155	#define CONFIG_SYS_MBAR 0xFC000000
	156
	157	/*
	158	* Low Level Configuration Settings
	159	* (address mappings, register initial values, etc.)
	160	* You should know what you are doing if you make changes here.
	161	*/
	162
	163	/*-----------------------------------------------------------------------
	164	* Definitions for initial stack pointer and data area (in DPRAM)
	165	*/
	166	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
	167	/* End of used area in internal SRAM */
	168	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
	169	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
186fc4db	170	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
627b73e2	171	GENERATED_GBL_DATA_SIZE) - 32)
186fc4db AW	172	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	173	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
	174
	175	/*-----------------------------------------------------------------------
	176	* Start addresses for the final memory configuration
	177	* (Set up by the startup code)
	178	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
	179	*/
	180	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	181	#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
	182
186fc4db AW	183	#define CONFIG_SYS_DRAM_TEST
	184
	185	#if defined(CONFIG_CF_SBF) \|\| defined(CONFIG_SYS_NAND_BOOT)
	186	#define CONFIG_SERIAL_BOOT
	187	#endif
	188
	189	#if defined(CONFIG_SERIAL_BOOT)
61a4392a	190	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
186fc4db AW	191	#else
	192	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	193	#endif
	194
	195	#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
	196	/* Reserve 256 kB for Monitor */
	197	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	198	/* Reserve 256 kB for malloc() */
	199	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	200
	201	/*
	202	* For booting Linux, the board info and command line data
	203	* have to be in the first 8 MB of memory, since this is
	204	* the maximum mapped by the Linux kernel during initialization ??
	205	*/
	206	/* Initial Memory map for Linux */
	207	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
	208	(CONFIG_SYS_SDRAM_SIZE << 20))
	209
	210	/* Configuration for environment
	211	* Environment is embedded in u-boot in the second sector of the flash
	212	*/
186fc4db	213
186fc4db AW	214	#undef CONFIG_ENV_OVERWRITE
	215
	216	/* FLASH organization */
	217	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	218
186fc4db AW	219	#ifdef CONFIG_SYS_FLASH_CFI
186fc4db AW	220
186fc4db AW	221	/* Max size that the board might have */
	222	#define CONFIG_SYS_FLASH_SIZE 0x1000000
	223	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	224	/* max number of memory banks */
	225	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	226	/* max number of sectors on one chip */
	227	#define CONFIG_SYS_MAX_FLASH_SECT 270
	228	/* "Real" (hardware) sectors protection */
186fc4db AW	229	#define CONFIG_SYS_FLASH_CHECKSUM
	230	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
	231	#else
	232	/* max number of sectors on one chip */
	233	#define CONFIG_SYS_MAX_FLASH_SECT 270
	234	/* max number of sectors on one chip */
	235	#define CONFIG_SYS_MAX_FLASH_BANKS 0
	236	#endif
	237
	238	/*
	239	* This is setting for JFFS2 support in u-boot.
	240	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	241	*/
	242	#ifdef CONFIG_CMD_JFFS2
	243	#define CONFIG_JFFS2_DEV "nand0"
	244	#define CONFIG_JFFS2_PART_OFFSET (0x800000)
186fc4db AW	245
	246	#endif
	247
186fc4db AW	248	/* Cache Configuration */
	249	#define CONFIG_SYS_CACHELINE_SIZE 16
	250	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
	251	CONFIG_SYS_INIT_RAM_SIZE - 8)
	252	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
	253	CONFIG_SYS_INIT_RAM_SIZE - 4)
	254	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
	255	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	256	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	257	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	258	CF_ACR_EN \| CF_ACR_SM_ALL)
	259	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_IEC \| \
	260	CF_CACR_ICINVA \| CF_CACR_EUSP)
	261	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	262	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	263	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	264
	265	#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
	266	CONFIG_SYS_INIT_RAM_SIZE - 12)
	267
	268	/*-----------------------------------------------------------------------
	269	* Memory bank definitions
	270	*/
	271	/*
	272	* CS0 - NOR Flash 16MB
	273	* CS1 - Available
	274	* CS2 - Available
	275	* CS3 - Available
	276	* CS4 - Available
	277	* CS5 - Available
	278	*/
	279
	280	/* Flash */
	281	#define CONFIG_SYS_CS0_BASE 0x00000000
	282	#define CONFIG_SYS_CS0_MASK 0x000F0101
	283	#define CONFIG_SYS_CS0_CTRL 0x00001D60
	284
	285	#endif /* _M54418TWR_H */