[people/ms/u-boot.git] / include / configs / M5475EVB.h

/*
 * Configuation settings for the Freescale MCF5475 board.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5475EVB_H
#define _M5475EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF547x_8x	/* define processor family */
#define CONFIG_M547x		/* define processor type */
#define CONFIG_M5475		/* define processor type */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#define CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB

#define CONFIG_SLTTMR

#define CONFIG_FSLDMAFEC
#ifdef CONFIG_FSLDMAFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_HAS_ETH1

#	define CONFIG_SYS_DMA_USE_INTSRAM	1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	32
#	define CONFIG_SYS_TX_ETH_BUFFER	48
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_PINMUX		0
#	define CONFIG_SYS_FEC1_MIIBASE		CONFIG_SYS_FEC0_IOBASE

#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */

#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE

#endif

#ifdef CONFIG_CMD_USB
#	define CONFIG_USB_OHCI_NEW
#	define CONFIG_USB_STORAGE

#	ifndef CONFIG_CMD_PCI
#		define CONFIG_CMD_PCI
#	endif
#	define CONFIG_PCI_OHCI
#	define CONFIG_DOS_PARTITION

#	undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#	undef CONFIG_SYS_USB_OHCI_CPU_INIT
#	define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
#	define CONFIG_SYS_USB_OHCI_SLOT_NAME		"isp1561"
#	define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00008F00
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	8

#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000

#define CONFIG_SYS_PCI_IO_BUS		0x71000000
#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE		0x01000000

#define CONFIG_SYS_PCI_CFG_BUS		0x70000000
#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
#endif

#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM

#ifdef CONFIG_MCFFEC
#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M547xEVB
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off bank 1;"			\
	"era ff800000 ff83ffff;"		\
	"cp.b ${loadaddr} ff800000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */
#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#ifdef CONFIG_CMD_KGDB
#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
#define CONFIG_SYS_LOAD_ADDR		0x00010000

#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2

#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_INTSRAM		(CONFIG_SYS_MBAR + 0x10000)
#define CONFIG_SYS_INTSRAMSZ		0x8000

/*#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x21
#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM1_CTRL	0x21
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_CFG1		0x73711630
#define CONFIG_SYS_SDRAM_CFG2		0x46770000
#define CONFIG_SYS_SDRAM_CTRL		0xE10B0000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x018D0000
#define CONFIG_SYS_SDRAM_DRVSTRENGTH	0x000002AA
#ifdef CONFIG_SYS_DRAMSZ1
#	define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
#else
#	define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_DRAMSZ
#endif

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#ifdef CONFIG_SYS_NOR1SZ
#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#	define CONFIG_SYS_FLASH_SIZE		((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#else
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_FLASH_SIZE		(CONFIG_SYS_BOOTSZ << 20)
#endif
#endif

/* Configuration for environment
 * Environment is not embedded in u-boot but at offset 0x40000 on the flash.
 * First time runing may have env crc error warning if there is
 * no correct environment on the flash.
 */
#define CONFIG_ENV_OFFSET		0x40000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_IS_IN_FLASH	1

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
					 CF_CACR_IDCM)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
					 CF_CACR_IEC | CF_CACR_ICINVA)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - NOR Flash
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0xFF800000
#define CONFIG_SYS_CS0_MASK		(((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS0_CTRL		0x00101980

#ifdef CONFIG_SYS_NOR1SZ
#define CONFIG_SYS_CS1_BASE		0xE0000000
#define CONFIG_SYS_CS1_MASK		(((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS1_CTRL		0x00101D80
#endif

#endif				/* _M5475EVB_H */
Commit	Line	Data
57a12720 TL	1	/*
	2	* Configuation settings for the Freescale MCF5475 board.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
57a12720 TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M5475EVB_H
	15	#define _M5475EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21	#define CONFIG_MCF547x_8x /* define processor family */
	22	#define CONFIG_M547x /* define processor type */
	23	#define CONFIG_M5475 /* define processor type */
	24
57a12720	25	#define CONFIG_MCFUART
6d0f6bcf	26	#define CONFIG_SYS_UART_PORT (0)
57a12720	27	#define CONFIG_BAUDRATE 115200
57a12720 TL	28
	29	#define CONFIG_HW_WATCHDOG
	30	#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
	31
	32	/* Command line configuration */
	33	#include <config_cmd_default.h>
	34
	35	#define CONFIG_CMD_CACHE
	36	#undef CONFIG_CMD_DATE
	37	#define CONFIG_CMD_ELF
	38	#define CONFIG_CMD_FLASH
	39	#define CONFIG_CMD_I2C
	40	#define CONFIG_CMD_MEMORY
	41	#define CONFIG_CMD_MISC
	42	#define CONFIG_CMD_MII
	43	#define CONFIG_CMD_NET
	44	#define CONFIG_CMD_PCI
	45	#define CONFIG_CMD_PING
	46	#define CONFIG_CMD_REGINFO
	47	#define CONFIG_CMD_USB
	48
	49	#define CONFIG_SLTTMR
	50
	51	#define CONFIG_FSLDMAFEC
	52	#ifdef CONFIG_FSLDMAFEC
57a12720	53	# define CONFIG_MII 1
0f3ba7e9	54	# define CONFIG_MII_INIT 1
57a12720 TL	55	# define CONFIG_HAS_ETH1
57a12720 TL	56
6d0f6bcf JCPV	57	# define CONFIG_SYS_DMA_USE_INTSRAM 1
	58	# define CONFIG_SYS_DISCOVER_PHY
	59	# define CONFIG_SYS_RX_ETH_BUFFER 32
	60	# define CONFIG_SYS_TX_ETH_BUFFER 48
	61	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57a12720	62
6d0f6bcf JCPV	63	# define CONFIG_SYS_FEC0_PINMUX 0
	64	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	65	# define CONFIG_SYS_FEC1_PINMUX 0
	66	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
57a12720	67
53677ef1	68	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	69	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	70	# ifndef CONFIG_SYS_DISCOVER_PHY
57a12720 TL	71	# define FECDUPLEX FULL
	72	# define FECSPEED _100BASET
	73	# else
6d0f6bcf JCPV	74	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	75	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57a12720	76	# endif
6d0f6bcf	77	# endif /* CONFIG_SYS_DISCOVER_PHY */
57a12720 TL	78
	79	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	80	# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
	81	# define CONFIG_IPADDR 192.162.1.2
	82	# define CONFIG_NETMASK 255.255.255.0
	83	# define CONFIG_SERVERIP 192.162.1.1
	84	# define CONFIG_GATEWAYIP 192.162.1.1
	85	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	86
	87	#endif
	88
	89	#ifdef CONFIG_CMD_USB
	90	# define CONFIG_USB_OHCI_NEW
	91	# define CONFIG_USB_STORAGE
	92
	93	# ifndef CONFIG_CMD_PCI
	94	# define CONFIG_CMD_PCI
	95	# endif
	96	# define CONFIG_PCI_OHCI
	97	# define CONFIG_DOS_PARTITION
	98
6d0f6bcf JCPV	99	# undef CONFIG_SYS_USB_OHCI_BOARD_INIT
	100	# undef CONFIG_SYS_USB_OHCI_CPU_INIT
	101	# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	102	# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
	103	# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
57a12720 TL	104	#endif
	105
	106	/* I2C */
00f792e0 HS	107	#define CONFIG_SYS_I2C
	108	#define CONFIG_SYS_I2C_FSL
	109	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	110	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	111	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
6d0f6bcf	112	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
57a12720 TL	113
	114	/* PCI */
	115	#ifdef CONFIG_CMD_PCI
	116	#define CONFIG_PCI 1
	117	#define CONFIG_PCI_PNP 1
f33fca22	118	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
57a12720	119
6d0f6bcf	120	#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
57a12720	121
6d0f6bcf JCPV	122	#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
	123	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
	124	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
57a12720	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_PCI_IO_BUS 0x71000000
	127	#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
	128	#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
57a12720	129
6d0f6bcf JCPV	130	#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
	131	#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
	132	#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
57a12720 TL	133	#endif
	134
	135	#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	136	#define CONFIG_UDP_CHECKSUM
	137
	138	#ifdef CONFIG_MCFFEC
	139	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	140	# define CONFIG_IPADDR 192.162.1.2
	141	# define CONFIG_NETMASK 255.255.255.0
	142	# define CONFIG_SERVERIP 192.162.1.1
	143	# define CONFIG_GATEWAYIP 192.162.1.1
	144	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	145	#endif /* FEC_ENET */
	146
	147	#define CONFIG_HOSTNAME M547xEVB
	148	#define CONFIG_EXTRA_ENV_SETTINGS \
	149	"netdev=eth0\0" \
	150	"loadaddr=10000\0" \
	151	"u-boot=u-boot.bin\0" \
	152	"load=tftp ${loadaddr) ${u-boot}\0" \
	153	"upd=run load; run prog\0" \
	154	"prog=prot off bank 1;" \
09933fb0	155	"era ff800000 ff83ffff;" \
57a12720 TL	156	"cp.b ${loadaddr} ff800000 ${filesize};"\
	157	"save\0" \
	158	""
	159
	160	#define CONFIG_PRAM 512 /* 512 KB */
6d0f6bcf JCPV	161	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	162	#define CONFIG_SYS_LONGHELP /* undef to save memory */
57a12720 TL	163
57a12720 TL	164	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	165	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
57a12720	166	#else
6d0f6bcf	167	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
57a12720 TL	168	#endif
57a12720 TL	169
6d0f6bcf JCPV	170	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	171	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	172	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	173	#define CONFIG_SYS_LOAD_ADDR 0x00010000
57a12720	174
6d0f6bcf JCPV	175	#define CONFIG_SYS_HZ 1000
	176	#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
	177	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
57a12720	178
6d0f6bcf JCPV	179	#define CONFIG_SYS_MBAR 0xF0000000
	180	#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
	181	#define CONFIG_SYS_INTSRAMSZ 0x8000
57a12720	182
6d0f6bcf	183	/#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)/
57a12720 TL	184
	185	/*
	186	* Low Level Configuration Settings
	187	* (address mappings, register initial values, etc.)
	188	* You should know what you are doing if you make changes here.
	189	*/
	190	/*-----------------------------------------------------------------------
	191	* Definitions for initial stack pointer and data area (in DPRAM)
	192	*/
6d0f6bcf	193	#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
553f0982	194	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
6d0f6bcf	195	#define CONFIG_SYS_INIT_RAM_CTRL 0x21
553f0982	196	#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
6d0f6bcf JCPV	197	#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
6d0f6bcf JCPV	198	#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
25ddd1fb	199	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
6d0f6bcf	200	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
57a12720 TL	201
	202	/*-----------------------------------------------------------------------
	203	* Start addresses for the final memory configuration
	204	* (Set up by the startup code)
6d0f6bcf	205	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
57a12720	206	*/
6d0f6bcf JCPV	207	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	208	#define CONFIG_SYS_SDRAM_CFG1 0x73711630
	209	#define CONFIG_SYS_SDRAM_CFG2 0x46770000
	210	#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
	211	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	212	#define CONFIG_SYS_SDRAM_MODE 0x018D0000
	213	#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
	214	#ifdef CONFIG_SYS_DRAMSZ1
	215	# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
57a12720	216	#else
6d0f6bcf	217	# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
57a12720 TL	218	#endif
57a12720 TL	219
6d0f6bcf JCPV	220	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
6d0f6bcf JCPV	221	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
57a12720	222
6d0f6bcf JCPV	223	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d0f6bcf JCPV	224	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
57a12720	225
6d0f6bcf	226	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
57a12720	227
09933fb0 JJ	228	/* Reserve 256 kB for malloc() */
09933fb0 JJ	229	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
57a12720 TL	230	/*
	231	* For booting Linux, the board info and command line data
	232	* have to be in the first 8 MB of memory, since this is
	233	* the maximum mapped by the Linux kernel during initialization ??
	234	*/
6d0f6bcf	235	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
57a12720 TL	236
	237	/*-----------------------------------------------------------------------
	238	* FLASH organization
	239	*/
6d0f6bcf JCPV	240	#define CONFIG_SYS_FLASH_CFI
	241	#ifdef CONFIG_SYS_FLASH_CFI
	242	# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
00b1883a	243	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	244	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	245	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	246	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	247	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	248	#ifdef CONFIG_SYS_NOR1SZ
	249	# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	250	# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
	251	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
57a12720	252	#else
6d0f6bcf JCPV	253	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	254	# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
57a12720 TL	255	#endif
	256	#endif
	257
	258	/* Configuration for environment
09933fb0 JJ	259	* Environment is not embedded in u-boot but at offset 0x40000 on the flash.
	260	* First time runing may have env crc error warning if there is
	261	* no correct environment on the flash.
57a12720	262	*/
09933fb0 JJ	263	#define CONFIG_ENV_OFFSET 0x40000
09933fb0 JJ	264	#define CONFIG_ENV_SECT_SIZE 0x10000
5a1aceb0	265	#define CONFIG_ENV_IS_IN_FLASH 1
57a12720 TL	266
	267	/*-----------------------------------------------------------------------
	268	* Cache Configuration
	269	*/
6d0f6bcf	270	#define CONFIG_SYS_CACHELINE_SIZE 16
57a12720	271
dd9f054e	272	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	273	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	274	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	275	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	276	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
	277	CF_CACR_IDCM)
	278	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	279	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	280	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	281	CF_ACR_EN \| CF_ACR_SM_ALL)
	282	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_BCINVA \| \
	283	CF_CACR_IEC \| CF_CACR_ICINVA)
	284	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	285	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	286	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	287
57a12720 TL	288	/*-----------------------------------------------------------------------
	289	* Chipselect bank definitions
	290	*/
	291	/*
	292	* CS0 - NOR Flash 1, 2, 4, or 8MB
	293	* CS1 - NOR Flash
	294	* CS2 - Available
	295	* CS3 - Available
	296	* CS4 - Available
	297	* CS5 - Available
	298	*/
6d0f6bcf JCPV	299	#define CONFIG_SYS_CS0_BASE 0xFF800000
	300	#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
	301	#define CONFIG_SYS_CS0_CTRL 0x00101980
	302
	303	#ifdef CONFIG_SYS_NOR1SZ
	304	#define CONFIG_SYS_CS1_BASE 0xE0000000
	305	#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
	306	#define CONFIG_SYS_CS1_CTRL 0x00101D80
57a12720 TL	307	#endif
	308
	309	#endif /* _M5475EVB_H */