[people/ms/u-boot.git] / include / configs / M5485EVB.h

/*
 * Configuation settings for the Freescale MCF5485 FireEngine board.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5485EVB_H
#define _M5485EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF547x_8x	/* define processor family */
#define CONFIG_M548x		/* define processor type */
#define CONFIG_M5485		/* define processor type */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

#define CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB

#define CONFIG_SLTTMR

#define CONFIG_FSLDMAFEC
#ifdef CONFIG_FSLDMAFEC
#	define CONFIG_NET_MULTI		1
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_HAS_ETH1

#	define CONFIG_SYS_DMA_USE_INTSRAM	1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	32
#	define CONFIG_SYS_TX_ETH_BUFFER	48
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_PINMUX		0
#	define CONFIG_SYS_FEC1_MIIBASE		CONFIG_SYS_FEC0_IOBASE

#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */

#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE

#endif

#ifdef CONFIG_CMD_USB
#	define CONFIG_USB_STORAGE
#	define CONFIG_DOS_PARTITION
#	define CONFIG_USB_OHCI_NEW
#	ifndef CONFIG_CMD_PCI
#		define CONFIG_CMD_PCI
#	endif
/*#	define CONFIG_PCI_OHCI*/
#	define CONFIG_SYS_USB_OHCI_REGS_BASE		0x80041000
#	define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
#	define CONFIG_SYS_USB_OHCI_SLOT_NAME		"isp1561"
#	define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#endif

/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hw support */
#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		80000
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x00008F00
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000

#define CONFIG_SYS_PCI_IO_BUS		0x71000000
#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE		0x01000000

#define CONFIG_SYS_PCI_CFG_BUS		0x70000000
#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
#endif

#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM

#define CONFIG_HOSTNAME		M548xEVB
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off bank 1;"			\
	"era ff800000 ff82ffff;"		\
	"cp.b ${loadaddr} ff800000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */
#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#ifdef CONFIG_CMD_KGDB
#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
#define CONFIG_SYS_LOAD_ADDR		0x00010000

#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2

#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_INTSRAM		(CONFIG_SYS_MBAR + 0x10000)
#define CONFIG_SYS_INTSRAMSZ		0x8000

/*#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x21
#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM1_CTRL	0x21
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_CFG1		0x73711630
#define CONFIG_SYS_SDRAM_CFG2		0x46770000
#define CONFIG_SYS_SDRAM_CTRL		0xE10B0000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x018D0000
#define CONFIG_SYS_SDRAM_DRVSTRENGTH	0x000002AA
#ifdef CONFIG_SYS_DRAMSZ1
#	define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
#else
#	define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_DRAMSZ
#endif

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#ifdef CONFIG_SYS_NOR1SZ
#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#	define CONFIG_SYS_FLASH_SIZE		((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#else
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_FLASH_SIZE		(CONFIG_SYS_BOOTSZ << 20)
#endif
#endif

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_OFFSET		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
					 CF_CACR_IDCM)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
					 CF_CACR_IEC | CF_CACR_ICINVA)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - NOR Flash
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0xFF800000
#define CONFIG_SYS_CS0_MASK		(((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS0_CTRL		0x00101980

#ifdef CONFIG_SYS_NOR1SZ
#define CONFIG_SYS_CS1_BASE		0xE0000000
#define CONFIG_SYS_CS1_MASK		(((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS1_CTRL		0x00101D80
#endif

#endif				/* _M5485EVB_H */
Commit	Line	Data
57a12720 TL	1	/*
	2	* Configuation settings for the Freescale MCF5485 FireEngine board.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
	30	#ifndef _M5485EVB_H
	31	#define _M5485EVB_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_MCF547x_8x /* define processor family */
	38	#define CONFIG_M548x /* define processor type */
	39	#define CONFIG_M5485 /* define processor type */
	40
57a12720	41	#define CONFIG_MCFUART
6d0f6bcf	42	#define CONFIG_SYS_UART_PORT (0)
57a12720	43	#define CONFIG_BAUDRATE 115200
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
57a12720 TL	45
	46	#define CONFIG_HW_WATCHDOG
	47	#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
	48
	49	/* Command line configuration */
	50	#include <config_cmd_default.h>
	51
	52	#define CONFIG_CMD_CACHE
	53	#undef CONFIG_CMD_DATE
	54	#define CONFIG_CMD_ELF
	55	#define CONFIG_CMD_FLASH
	56	#define CONFIG_CMD_I2C
	57	#define CONFIG_CMD_MEMORY
	58	#define CONFIG_CMD_MISC
	59	#define CONFIG_CMD_MII
	60	#define CONFIG_CMD_NET
	61	#define CONFIG_CMD_PCI
	62	#define CONFIG_CMD_PING
	63	#define CONFIG_CMD_REGINFO
	64	#define CONFIG_CMD_USB
	65
	66	#define CONFIG_SLTTMR
	67
	68	#define CONFIG_FSLDMAFEC
	69	#ifdef CONFIG_FSLDMAFEC
	70	# define CONFIG_NET_MULTI 1
	71	# define CONFIG_MII 1
0f3ba7e9	72	# define CONFIG_MII_INIT 1
57a12720 TL	73	# define CONFIG_HAS_ETH1
57a12720 TL	74
6d0f6bcf JCPV	75	# define CONFIG_SYS_DMA_USE_INTSRAM 1
	76	# define CONFIG_SYS_DISCOVER_PHY
	77	# define CONFIG_SYS_RX_ETH_BUFFER 32
	78	# define CONFIG_SYS_TX_ETH_BUFFER 48
	79	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57a12720	80
6d0f6bcf JCPV	81	# define CONFIG_SYS_FEC0_PINMUX 0
	82	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	83	# define CONFIG_SYS_FEC1_PINMUX 0
	84	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
57a12720	85
53677ef1	86	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	87	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	88	# ifndef CONFIG_SYS_DISCOVER_PHY
57a12720 TL	89	# define FECDUPLEX FULL
	90	# define FECSPEED _100BASET
	91	# else
6d0f6bcf JCPV	92	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	93	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57a12720	94	# endif
6d0f6bcf	95	# endif /* CONFIG_SYS_DISCOVER_PHY */
57a12720 TL	96
	97	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	98	# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
	99	# define CONFIG_IPADDR 192.162.1.2
	100	# define CONFIG_NETMASK 255.255.255.0
	101	# define CONFIG_SERVERIP 192.162.1.1
	102	# define CONFIG_GATEWAYIP 192.162.1.1
	103	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	104
	105	#endif
	106
	107	#ifdef CONFIG_CMD_USB
	108	# define CONFIG_USB_STORAGE
	109	# define CONFIG_DOS_PARTITION
	110	# define CONFIG_USB_OHCI_NEW
	111	# ifndef CONFIG_CMD_PCI
	112	# define CONFIG_CMD_PCI
	113	# endif
	114	/# define CONFIG_PCI_OHCI/
6d0f6bcf JCPV	115	# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
	116	# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	117	# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
	118	# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
57a12720 TL	119	#endif
	120
	121	/* I2C */
	122	#define CONFIG_FSL_I2C
	123	#define CONFIG_HARD_I2C /* I2C with hw support */
	124	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	125	#define CONFIG_SYS_I2C_SPEED 80000
	126	#define CONFIG_SYS_I2C_SLAVE 0x7F
	127	#define CONFIG_SYS_I2C_OFFSET 0x00008F00
	128	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
57a12720 TL	129
	130	/* PCI */
	131	#ifdef CONFIG_CMD_PCI
	132	#define CONFIG_PCI 1
	133	#define CONFIG_PCI_PNP 1
f33fca22	134	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
57a12720	135
6d0f6bcf JCPV	136	#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
	137	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
	138	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
57a12720	139
6d0f6bcf JCPV	140	#define CONFIG_SYS_PCI_IO_BUS 0x71000000
	141	#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
	142	#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
57a12720	143
6d0f6bcf JCPV	144	#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
	145	#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
	146	#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
57a12720 TL	147	#endif
	148
	149	#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	150	#define CONFIG_UDP_CHECKSUM
	151
	152	#define CONFIG_HOSTNAME M548xEVB
	153	#define CONFIG_EXTRA_ENV_SETTINGS \
	154	"netdev=eth0\0" \
	155	"loadaddr=10000\0" \
	156	"u-boot=u-boot.bin\0" \
	157	"load=tftp ${loadaddr) ${u-boot}\0" \
	158	"upd=run load; run prog\0" \
	159	"prog=prot off bank 1;" \
	160	"era ff800000 ff82ffff;" \
	161	"cp.b ${loadaddr} ff800000 ${filesize};"\
	162	"save\0" \
	163	""
	164
	165	#define CONFIG_PRAM 512 /* 512 KB */
6d0f6bcf JCPV	166	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	167	#define CONFIG_SYS_LONGHELP /* undef to save memory */
57a12720 TL	168
57a12720 TL	169	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	170	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
57a12720	171	#else
6d0f6bcf	172	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
57a12720 TL	173	#endif
57a12720 TL	174
6d0f6bcf JCPV	175	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	176	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	177	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	178	#define CONFIG_SYS_LOAD_ADDR 0x00010000
57a12720	179
6d0f6bcf JCPV	180	#define CONFIG_SYS_HZ 1000
	181	#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
	182	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
57a12720	183
6d0f6bcf JCPV	184	#define CONFIG_SYS_MBAR 0xF0000000
	185	#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
	186	#define CONFIG_SYS_INTSRAMSZ 0x8000
57a12720	187
6d0f6bcf	188	/#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)/
57a12720 TL	189
	190	/*
	191	* Low Level Configuration Settings
	192	* (address mappings, register initial values, etc.)
	193	* You should know what you are doing if you make changes here.
	194	*/
	195	/*-----------------------------------------------------------------------
	196	* Definitions for initial stack pointer and data area (in DPRAM)
	197	*/
6d0f6bcf	198	#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
553f0982	199	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
6d0f6bcf	200	#define CONFIG_SYS_INIT_RAM_CTRL 0x21
553f0982	201	#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
6d0f6bcf JCPV	202	#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
	203	#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
	204	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
553f0982	205	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
6d0f6bcf	206	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
57a12720 TL	207
	208	/*-----------------------------------------------------------------------
	209	* Start addresses for the final memory configuration
	210	* (Set up by the startup code)
6d0f6bcf	211	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
57a12720	212	*/
6d0f6bcf JCPV	213	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	214	#define CONFIG_SYS_SDRAM_CFG1 0x73711630
	215	#define CONFIG_SYS_SDRAM_CFG2 0x46770000
	216	#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
	217	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	218	#define CONFIG_SYS_SDRAM_MODE 0x018D0000
	219	#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
	220	#ifdef CONFIG_SYS_DRAMSZ1
	221	# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
57a12720	222	#else
6d0f6bcf	223	# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
57a12720 TL	224	#endif
57a12720 TL	225
6d0f6bcf JCPV	226	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
6d0f6bcf JCPV	227	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
57a12720	228
6d0f6bcf JCPV	229	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d0f6bcf JCPV	230	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
57a12720	231
6d0f6bcf JCPV	232	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	233	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
57a12720 TL	234
	235	/*
	236	* For booting Linux, the board info and command line data
	237	* have to be in the first 8 MB of memory, since this is
	238	* the maximum mapped by the Linux kernel during initialization ??
	239	*/
6d0f6bcf	240	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
57a12720 TL	241
	242	/*-----------------------------------------------------------------------
	243	* FLASH organization
	244	*/
6d0f6bcf JCPV	245	#define CONFIG_SYS_FLASH_CFI
	246	#ifdef CONFIG_SYS_FLASH_CFI
	247	# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
00b1883a	248	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	249	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	250	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	251	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	252	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	253	#ifdef CONFIG_SYS_NOR1SZ
	254	# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	255	# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
	256	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
57a12720	257	#else
6d0f6bcf JCPV	258	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	259	# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
57a12720 TL	260	#endif
	261	#endif
	262
	263	/* Configuration for environment
	264	* Environment is embedded in u-boot in the second sector of the flash
	265	*/
0e8d1586 JCPV	266	#define CONFIG_ENV_OFFSET 0x2000
0e8d1586 JCPV	267	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	268	#define CONFIG_ENV_IS_IN_FLASH 1
57a12720 TL	269
	270	/*-----------------------------------------------------------------------
	271	* Cache Configuration
	272	*/
6d0f6bcf	273	#define CONFIG_SYS_CACHELINE_SIZE 16
57a12720	274
dd9f054e	275	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	276	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	277	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	278	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	279	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
	280	CF_CACR_IDCM)
	281	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	282	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	283	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	284	CF_ACR_EN \| CF_ACR_SM_ALL)
	285	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_BCINVA \| \
	286	CF_CACR_IEC \| CF_CACR_ICINVA)
	287	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	288	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	289	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	290
57a12720 TL	291	/*-----------------------------------------------------------------------
	292	* Chipselect bank definitions
	293	*/
	294	/*
	295	* CS0 - NOR Flash 1, 2, 4, or 8MB
	296	* CS1 - NOR Flash
	297	* CS2 - Available
	298	* CS3 - Available
	299	* CS4 - Available
	300	* CS5 - Available
	301	*/
6d0f6bcf JCPV	302	#define CONFIG_SYS_CS0_BASE 0xFF800000
	303	#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
	304	#define CONFIG_SYS_CS0_CTRL 0x00101980
	305
	306	#ifdef CONFIG_SYS_NOR1SZ
	307	#define CONFIG_SYS_CS1_BASE 0xE0000000
	308	#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
	309	#define CONFIG_SYS_CS1_CTRL 0x00101D80
57a12720 TL	310	#endif
	311
	312	#endif /* _M5485EVB_H */