[thirdparty/u-boot.git] / include / configs / M5485EVB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for the Freescale MCF5485 FireEngine board.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5485EVB_H
#define _M5485EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */

#define CONFIG_SLTTMR

#define CONFIG_FSLDMAFEC
#ifdef CONFIG_FSLDMAFEC
#	define CONFIG_MII_INIT		1
#	define CONFIG_HAS_ETH1

#	define CONFIG_SYS_DMA_USE_INTSRAM	1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	32
#	define CONFIG_SYS_TX_ETH_BUFFER	48
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_PINMUX		0
#	define CONFIG_SYS_FEC1_MIIBASE		CONFIG_SYS_FEC0_IOBASE

#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */

#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1

#endif

#ifdef CONFIG_CMD_USB
#	define CONFIG_USB_OHCI_NEW
/*#	define CONFIG_PCI_OHCI*/
#	define CONFIG_SYS_USB_OHCI_REGS_BASE		0x80041000
#	define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
#	define CONFIG_SYS_USB_OHCI_SLOT_NAME		"isp1561"
#	define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00008F00
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000

#define CONFIG_SYS_PCI_IO_BUS		0x71000000
#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE		0x01000000

#define CONFIG_SYS_PCI_CFG_BUS		0x70000000
#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
#endif

#define CONFIG_UDP_CHECKSUM

#define CONFIG_HOSTNAME		"M548xEVB"
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off bank 1;"			\
	"era ff800000 ff83ffff;"		\
	"cp.b ${loadaddr} ff800000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */

#define CONFIG_SYS_LOAD_ADDR		0x00010000

#define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2

#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_INTSRAM		(CONFIG_SYS_MBAR + 0x10000)
#define CONFIG_SYS_INTSRAMSZ		0x8000

/*#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x21
#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM1_CTRL	0x21
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_CFG1		0x73711630
#define CONFIG_SYS_SDRAM_CFG2		0x46770000
#define CONFIG_SYS_SDRAM_CTRL		0xE10B0000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x018D0000
#define CONFIG_SYS_SDRAM_DRVSTRENGTH	0x000002AA
#ifdef CONFIG_SYS_DRAMSZ1
#	define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
#else
#	define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_DRAMSZ
#endif

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#ifdef CONFIG_SYS_NOR1SZ
#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#	define CONFIG_SYS_FLASH_SIZE		((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#else
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_FLASH_SIZE		(CONFIG_SYS_BOOTSZ << 20)
#endif
#endif

/* Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#define CONFIG_ENV_OFFSET		0x40000
#define CONFIG_ENV_SECT_SIZE	0x10000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
					 CF_CACR_IDCM)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
					 CF_CACR_IEC | CF_CACR_ICINVA)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - NOR Flash
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0xFF800000
#define CONFIG_SYS_CS0_MASK		(((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS0_CTRL		0x00101980

#ifdef CONFIG_SYS_NOR1SZ
#define CONFIG_SYS_CS1_BASE		0xE0000000
#define CONFIG_SYS_CS1_MASK		(((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS1_CTRL		0x00101D80
#endif

#endif				/* _M5485EVB_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
57a12720 TL	2	/*
	3	* Configuation settings for the Freescale MCF5485 FireEngine board.
	4	*
	5	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
57a12720 TL	7	*/
	8
	9	/*
	10	* board/config.h - configuration options, board specific
	11	*/
	12
	13	#ifndef _M5485EVB_H
	14	#define _M5485EVB_H
	15
	16	/*
	17	* High Level Configuration Options
	18	* (easy to change)
	19	*/
57a12720	20
57a12720	21	#define CONFIG_MCFUART
6d0f6bcf	22	#define CONFIG_SYS_UART_PORT (0)
57a12720	23
1313db48	24	#undef CONFIG_HW_WATCHDOG
57a12720 TL	25	#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
57a12720 TL	26
57a12720 TL	27	#define CONFIG_SLTTMR
	28
	29	#define CONFIG_FSLDMAFEC
	30	#ifdef CONFIG_FSLDMAFEC
0f3ba7e9	31	# define CONFIG_MII_INIT 1
57a12720 TL	32	# define CONFIG_HAS_ETH1
57a12720 TL	33
6d0f6bcf JCPV	34	# define CONFIG_SYS_DMA_USE_INTSRAM 1
	35	# define CONFIG_SYS_DISCOVER_PHY
	36	# define CONFIG_SYS_RX_ETH_BUFFER 32
	37	# define CONFIG_SYS_TX_ETH_BUFFER 48
	38	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57a12720	39
6d0f6bcf JCPV	40	# define CONFIG_SYS_FEC0_PINMUX 0
	41	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	42	# define CONFIG_SYS_FEC1_PINMUX 0
	43	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
57a12720	44
53677ef1	45	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	46	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	47	# ifndef CONFIG_SYS_DISCOVER_PHY
57a12720 TL	48	# define FECDUPLEX FULL
	49	# define FECSPEED _100BASET
	50	# else
6d0f6bcf JCPV	51	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	52	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57a12720	53	# endif
6d0f6bcf	54	# endif /* CONFIG_SYS_DISCOVER_PHY */
57a12720	55
57a12720 TL	56	# define CONFIG_IPADDR 192.162.1.2
	57	# define CONFIG_NETMASK 255.255.255.0
	58	# define CONFIG_SERVERIP 192.162.1.1
	59	# define CONFIG_GATEWAYIP 192.162.1.1
57a12720 TL	60
	61	#endif
	62
	63	#ifdef CONFIG_CMD_USB
57a12720	64	# define CONFIG_USB_OHCI_NEW
57a12720	65	/# define CONFIG_PCI_OHCI/
6d0f6bcf JCPV	66	# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
	67	# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	68	# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
	69	# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
57a12720 TL	70	#endif
	71
	72	/* I2C */
00f792e0 HS	73	#define CONFIG_SYS_I2C
	74	#define CONFIG_SYS_I2C_FSL
	75	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	76	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	77	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
6d0f6bcf	78	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
57a12720 TL	79
	80	/* PCI */
	81	#ifdef CONFIG_CMD_PCI
f33fca22	82	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
57a12720	83
6d0f6bcf JCPV	84	#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
	85	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
	86	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
57a12720	87
6d0f6bcf JCPV	88	#define CONFIG_SYS_PCI_IO_BUS 0x71000000
	89	#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
	90	#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
57a12720	91
6d0f6bcf JCPV	92	#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
	93	#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
	94	#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
57a12720 TL	95	#endif
57a12720 TL	96
57a12720 TL	97	#define CONFIG_UDP_CHECKSUM
57a12720 TL	98
5bc0543d	99	#define CONFIG_HOSTNAME "M548xEVB"
57a12720 TL	100	#define CONFIG_EXTRA_ENV_SETTINGS \
	101	"netdev=eth0\0" \
	102	"loadaddr=10000\0" \
	103	"u-boot=u-boot.bin\0" \
	104	"load=tftp ${loadaddr) ${u-boot}\0" \
	105	"upd=run load; run prog\0" \
	106	"prog=prot off bank 1;" \
09933fb0	107	"era ff800000 ff83ffff;" \
57a12720 TL	108	"cp.b ${loadaddr} ff800000 ${filesize};"\
	109	"save\0" \
	110	""
	111
	112	#define CONFIG_PRAM 512 /* 512 KB */
57a12720	113
6d0f6bcf	114	#define CONFIG_SYS_LOAD_ADDR 0x00010000
57a12720	115
6d0f6bcf JCPV	116	#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
6d0f6bcf JCPV	117	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
57a12720	118
6d0f6bcf JCPV	119	#define CONFIG_SYS_MBAR 0xF0000000
	120	#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
	121	#define CONFIG_SYS_INTSRAMSZ 0x8000
57a12720	122
6d0f6bcf	123	/#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)/
57a12720 TL	124
	125	/*
	126	* Low Level Configuration Settings
	127	* (address mappings, register initial values, etc.)
	128	* You should know what you are doing if you make changes here.
	129	*/
	130	/*-----------------------------------------------------------------------
	131	* Definitions for initial stack pointer and data area (in DPRAM)
	132	*/
6d0f6bcf	133	#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
553f0982	134	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
6d0f6bcf	135	#define CONFIG_SYS_INIT_RAM_CTRL 0x21
553f0982	136	#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
6d0f6bcf JCPV	137	#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
6d0f6bcf JCPV	138	#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
25ddd1fb	139	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
6d0f6bcf	140	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
57a12720 TL	141
	142	/*-----------------------------------------------------------------------
	143	* Start addresses for the final memory configuration
	144	* (Set up by the startup code)
6d0f6bcf	145	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
57a12720	146	*/
6d0f6bcf JCPV	147	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	148	#define CONFIG_SYS_SDRAM_CFG1 0x73711630
	149	#define CONFIG_SYS_SDRAM_CFG2 0x46770000
	150	#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
	151	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	152	#define CONFIG_SYS_SDRAM_MODE 0x018D0000
	153	#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
	154	#ifdef CONFIG_SYS_DRAMSZ1
	155	# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
57a12720	156	#else
6d0f6bcf	157	# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
57a12720 TL	158	#endif
57a12720 TL	159
6d0f6bcf JCPV	160	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
6d0f6bcf JCPV	161	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
57a12720	162
6d0f6bcf JCPV	163	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d0f6bcf JCPV	164	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
57a12720	165
6d0f6bcf	166	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
57a12720	167
09933fb0 JJ	168	/* Reserve 256 kB for malloc() */
09933fb0 JJ	169	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
57a12720 TL	170	/*
	171	* For booting Linux, the board info and command line data
	172	* have to be in the first 8 MB of memory, since this is
	173	* the maximum mapped by the Linux kernel during initialization ??
	174	*/
6d0f6bcf	175	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
57a12720 TL	176
	177	/*-----------------------------------------------------------------------
	178	* FLASH organization
	179	*/
6d0f6bcf JCPV	180	#define CONFIG_SYS_FLASH_CFI
	181	#ifdef CONFIG_SYS_FLASH_CFI
	182	# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
00b1883a	183	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	184	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	185	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	186	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	187	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	188	#ifdef CONFIG_SYS_NOR1SZ
	189	# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	190	# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
	191	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
57a12720	192	#else
6d0f6bcf JCPV	193	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	194	# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
57a12720 TL	195	#endif
	196	#endif
	197
	198	/* Configuration for environment
09933fb0 JJ	199	* Environment is not embedded in u-boot. First time runing may have env
09933fb0 JJ	200	* crc error warning if there is no correct environment on the flash.
57a12720	201	*/
09933fb0 JJ	202	#define CONFIG_ENV_OFFSET 0x40000
09933fb0 JJ	203	#define CONFIG_ENV_SECT_SIZE 0x10000
57a12720 TL	204
	205	/*-----------------------------------------------------------------------
	206	* Cache Configuration
	207	*/
6d0f6bcf	208	#define CONFIG_SYS_CACHELINE_SIZE 16
57a12720	209
dd9f054e	210	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	211	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	212	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	213	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	214	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
	215	CF_CACR_IDCM)
	216	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	217	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	218	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	219	CF_ACR_EN \| CF_ACR_SM_ALL)
	220	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_BCINVA \| \
	221	CF_CACR_IEC \| CF_CACR_ICINVA)
	222	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	223	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	224	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	225
57a12720 TL	226	/*-----------------------------------------------------------------------
	227	* Chipselect bank definitions
	228	*/
	229	/*
	230	* CS0 - NOR Flash 1, 2, 4, or 8MB
	231	* CS1 - NOR Flash
	232	* CS2 - Available
	233	* CS3 - Available
	234	* CS4 - Available
	235	* CS5 - Available
	236	*/
6d0f6bcf JCPV	237	#define CONFIG_SYS_CS0_BASE 0xFF800000
	238	#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
	239	#define CONFIG_SYS_CS0_CTRL 0x00101980
	240
	241	#ifdef CONFIG_SYS_NOR1SZ
	242	#define CONFIG_SYS_CS1_BASE 0xE0000000
	243	#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
	244	#define CONFIG_SYS_CS1_CTRL 0x00101D80
57a12720 TL	245	#endif
	246
	247	#endif /* _M5485EVB_H */