[people/ms/u-boot.git] / include / configs / MBX.h

/*
 * (C) Copyright 2000
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Configuation settings for the MBX8xx board.
 *
 * -----------------------------------------------------------------
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
/*
 * Changed 2002-10-01
 * Added PCMCIA defines mostly taken from other U-Boot boards that
 * have PCMCIA already working.  If you find any bugs, incorrect assumptions
 * feel free to fix them yourself and submit a patch.
 * Rod Boyce <rod_boyce@stratexnet.com.
 */
/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
#define CONFIG_MBX		1	/* ...on an MBX module		*/

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600
/* Define this to use the PCI bus */
#undef CONFIG_USE_PCI

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
#define CONFIG_8xx_GCLK_FREQ    (50000000UL)
#if 1
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootm 20000" /* autoboot command	*/

#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
				"nfsaddrs=10.0.0.99:10.0.0.2"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE   /* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_IDE


#define CONFIG_DOS_PARTITION

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#undef	CFG_HUSH_PARSER			/* Hush parse for U-Boot	*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Physical memory map as defined by the MBX PGM
 */
#define CFG_IMMR		0xFA200000 /* Internal Memory Mapped Register*/
#define CFG_NVRAM_BASE		0xFA000000 /* NVRAM			     */
#define CFG_NVRAM_OR		0xffe00000 /* w/o speed dependent flags!!    */
#define CFG_CSR_BASE		0xFA100000 /* Control/Status Registers	     */
#define CFG_PCIMEM_BASE		0x80000000 /* PCI I/O and Memory Spaces	     */
#define CFG_PCIMEM_OR		0xA0000108
#define CFG_PCIBRIDGE_BASE	0xFA210000 /* PCI-Bus Bridge Registers	     */
#define CFG_PCIBRIDGE_OR	0xFFFF0108

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
#define CFG_INIT_VPD_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
#define CFG_INIT_SP_OFFSET	(CFG_INIT_VPD_OFFSET-8)

/*-----------------------------------------------------------------------
 * Offset in DPMEM where we keep the VPD data
 */
#define CFG_DPRAMVPD		(CFG_INIT_VPD_OFFSET - 0x2000)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xfe000000
#ifdef	DEBUG
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#endif
#undef	CFG_MONITOR_BASE	/* 0x200000	   to run U-Boot from RAM */
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * NVRAM Configuration
 *
 * Note: the MBX is special because there is already a firmware on this
 * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
 * access the NVRAM at the offset 0x1000.
 */
#define CONFIG_ENV_IS_IN_NVRAM	1	/* turn on NVRAM env feature */
#define CONFIG_ENV_ADDR		(CFG_NVRAM_BASE + 0x1000)
#define CONFIG_ENV_SIZE		0x1000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
/* #define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)
#define CFG_SCCR	SCCR_TBS

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

#define CFG_PCMCIA_INTERRUPT	SIU_LEVEL6

#define CONFIG_PCMCIA_SLOT_A	1


/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 * Debug Entry Mode
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER 0

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2000
	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Marius Groeger <mgroeger@sysgo.de>
	5	*
	6	* Configuation settings for the MBX8xx board.
	7	*
	8	* -----------------------------------------------------------------
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27	/*
	28	* Changed 2002-10-01
	29	* Added PCMCIA defines mostly taken from other U-Boot boards that
	30	* have PCMCIA already working. If you find any bugs, incorrect assumptions
	31	* feel free to fix them yourself and submit a patch.
	32	* Rod Boyce <rod_boyce@stratexnet.com.
	33	*/
	34	/*
	35	* board/config.h - configuration options, board specific
	36	*/
	37
	38	#ifndef __CONFIG_H
	39	#define __CONFIG_H
	40
	41	/*
	42	* High Level Configuration Options
	43	* (easy to change)
	44	*/
	45
	46	#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
	47	#define CONFIG_MBX 1 /* ...on an MBX module */
	48
	49	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	50	#undef CONFIG_8xx_CONS_SMC2
	51	#undef CONFIG_8xx_CONS_NONE
	52	#define CONFIG_BAUDRATE 9600
	53	/* Define this to use the PCI bus */
	54	#undef CONFIG_USE_PCI
	55
	56	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	57	#define CONFIG_8xx_GCLK_FREQ (50000000UL)
	58	#if 1
	59	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	60	#else
	61	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	62	#endif
	63	#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */
	64
65	#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
66	"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
67	"nfsaddrs=10.0.0.99:10.0.0.2"
68
69	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
70	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
71
72	#undef CONFIG_WATCHDOG /* watchdog disabled */
73
e2211743	74
659e2f67 JL	75	/*
	76	* BOOTP options
	77	*/
	78	#define CONFIG_BOOTP_BOOTFILESIZE
	79	#define CONFIG_BOOTP_BOOTPATH
	80	#define CONFIG_BOOTP_GATEWAY
	81	#define CONFIG_BOOTP_HOSTNAME
	82
	83
8353e139 JL	84	/*
	85	* Command line configuration.
	86	*/
	87	#define CONFIG_CMD_NET
	88	#define CONFIG_CMD_DFL
	89	#define CONFIG_CMD_SDRAM
	90	#define CONFIG_CMD_PCMCIA
	91	#define CONFIG_CMD_IDE
e2211743	92
8353e139 JL	93
8353e139 JL	94	#define CONFIG_DOS_PARTITION
e2211743 WD	95
	96	/*
	97	* Miscellaneous configurable options
	98	*/
	99	#define CFG_LONGHELP /* undef to save memory */
	100	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	101	#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */
	102	#ifdef CFG_HUSH_PARSER
	103	#define CFG_PROMPT_HUSH_PS2 "> "
	104	#endif
8353e139	105	#if defined(CONFIG_CMD_KGDB)
e2211743 WD	106	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	107	#else
	108	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	109	#endif
	110	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	111	#define CFG_MAXARGS 16 /* max number of command args */
	112	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	113
	114	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	115	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	116
	117	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	118
	119	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	120
	121	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	122
	123	/*
	124	* Low Level Configuration Settings
	125	* (address mappings, register initial values, etc.)
	126	* You should know what you are doing if you make changes here.
	127	*/
	128
	129	/*-----------------------------------------------------------------------
	130	* Physical memory map as defined by the MBX PGM
	131	*/
	132	#define CFG_IMMR 0xFA200000 /* Internal Memory Mapped Register*/
	133	#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */
	134	#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
	135	#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */
	136	#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
	137	#define CFG_PCIMEM_OR 0xA0000108
	138	#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
	139	#define CFG_PCIBRIDGE_OR 0xFFFF0108
	140
	141	/*-----------------------------------------------------------------------
	142	* Definitions for initial stack pointer and data area (in DPRAM)
	143	*/
	144	#define CFG_INIT_RAM_ADDR CFG_IMMR
	145	#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
	146	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	147	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	148	#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
	149	#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
	150	#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8)
	151
	152	/*-----------------------------------------------------------------------
	153	* Offset in DPMEM where we keep the VPD data
	154	*/
	155	#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000)
	156
	157	/*-----------------------------------------------------------------------
	158	* Start addresses for the final memory configuration
	159	* (Set up by the startup code)
	160	* Please note that CFG_SDRAM_BASE _must_ start at 0
	161	*/
	162	#define CFG_SDRAM_BASE 0x00000000
	163	#define CFG_FLASH_BASE 0xfe000000
	164	#ifdef DEBUG
	165	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	166	#else
	167	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	168	#endif
	169	#undef CFG_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */
170	#define CFG_MONITOR_BASE CFG_FLASH_BASE
171	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
172
173	/*
174	* For booting Linux, the board info and command line data
175	* have to be in the first 8 MB of memory, since this is
176	* the maximum mapped by the Linux kernel during initialization.
177	*/
178	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
179
180	/*-----------------------------------------------------------------------
181	* FLASH organization
182	*/
183	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
184	#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
185
186	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
187	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
188
189	/*-----------------------------------------------------------------------
190	* NVRAM Configuration
191	*
192	* Note: the MBX is special because there is already a firmware on this
193	* board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
194	* access the NVRAM at the offset 0x1000.
195	*/
9314cee6	196	#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
0e8d1586 JCPV	197	#define CONFIG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000)
0e8d1586 JCPV	198	#define CONFIG_ENV_SIZE 0x1000
e2211743 WD	199
	200	/*-----------------------------------------------------------------------
	201	* Cache Configuration
	202	*/
	203	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
8353e139	204	#if defined(CONFIG_CMD_KGDB)
e2211743 WD	205	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	206	#endif
	207
	208	/*-----------------------------------------------------------------------
	209	* SYPCR - System Protection Control 11-9
	210	* SYPCR can only be written once after reset!
	211	*-----------------------------------------------------------------------
	212	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	213	*/
	214	#if defined(CONFIG_WATCHDOG)
	215	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	216	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	217	#else
	218	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF)
	219	#endif
	220
	221	/*-----------------------------------------------------------------------
	222	* SIUMCR - SIU Module Configuration 11-6
	223	*-----------------------------------------------------------------------
	224	* PCMCIA config., multi-function pin tri-state
	225	*/
	226	/* #define CFG_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DPC \| SIUMCR_MLRC10 \| SIUMCR_SEME) */
	227	#define CFG_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DPC \| SIUMCR_MLRC11 \| SIUMCR_SEME \| SIUMCR_BSC )
	228
	229	/*-----------------------------------------------------------------------
	230	* TBSCR - Time Base Status and Control 11-26
	231	*-----------------------------------------------------------------------
	232	* Clear Reference Interrupt Status, Timebase freezing enabled
	233	*/
	234	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	235
	236	/*-----------------------------------------------------------------------
	237	* PISCR - Periodic Interrupt Status and Control 11-31
	238	*-----------------------------------------------------------------------
	239	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	240	*/
	241	#define CFG_PISCR (PISCR_PS \| PISCR_PITF \| PISCR_PTE)
	242
	243	/*-----------------------------------------------------------------------
	244	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	245	*-----------------------------------------------------------------------
	246	* Reset PLL lock status sticky bit, timer expired status bit and timer
	247	* interrupt status bit - leave PLL multiplication factor unchanged !
	248	*/
	249	#define CFG_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
	250
	251	/*-----------------------------------------------------------------------
	252	* SCCR - System Clock and reset Control Register 15-27
	253	*-----------------------------------------------------------------------
	254	* Set clock output, timebase and RTC source and divider,
	255	* power management and some other internal clocks
	256	*/
	257	#define SCCR_MASK (SCCR_RTDIV \| SCCR_RTSEL)
	258	#define CFG_SCCR SCCR_TBS
	259
	260	/*-----------------------------------------------------------------------
	261	* PCMCIA stuff
	262	*-----------------------------------------------------------------------
	263	*
	264	*/
	265	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
	266	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
	267	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
	268	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
269	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
270	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
271	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
272	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
273
274	#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
275
276	#define CONFIG_PCMCIA_SLOT_A 1
277
278
279	/*-----------------------------------------------------------------------
280	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
281	*-----------------------------------------------------------------------
282	*/
283
284	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
285
286	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
287	#undef CONFIG_IDE_LED /* LED for ide not supported */
288	#undef CONFIG_IDE_RESET /* reset for ide not supported */
289
290	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
291	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
292
293	#define CFG_ATA_IDE0_OFFSET 0x0000
294
295	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
296
297	/* Offset for data I/O */
298	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
299
300	/* Offset for normal register accesses */
301	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
302
303	/* Offset for alternate registers */
304	#define CFG_ATA_ALT_OFFSET 0x0100
305
306	/*-----------------------------------------------------------------------
307	* Debug Entry Mode
308	*-----------------------------------------------------------------------
309	*
310	*/
311	#define CFG_DER 0
312
313	/*
314	* Internal Definitions
315	*
316	* Boot Flags
317	*/
318	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
319	#define BOOTFLAG_WARM 0x02 /* Software reboot */
320
321	#endif /* __CONFIG_H */