[people/ms/u-boot.git] / include / configs / METROBOX.h

/*
 * (C) Copyright 2004 Sandburst Corporation
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * METROBOX.h - configuration Sandburst MetroBox
 ***********************************************************************/

/*
 * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
 *
 *
 * $Log: METROBOX.h,v $
 * Revision 1.21  2005/06/03 15:05:25  tsawyer
 * MB rev 2.0.3 KA rev 0.0.7.  Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
 *
 * Revision 1.20  2005/04/11 20:51:11  tsawyer
 * fix ethernet
 *
 * Revision 1.19  2005/04/06 15:13:36  tsawyer
 * Update appropriate files to coincide with u-boot 1.1.3
 *
 * Revision 1.18  2005/03/10 14:16:02  tsawyer
 * add def'n for cis8201 short etch option.
 *
 * Revision 1.17  2005/03/09 19:49:51  tsawyer
 * Remove KGDB to allow use of 2nd serial port
 *
 * Revision 1.16  2004/12/02 19:00:23  tsawyer
 * Add misc_init_f to turn on i2c-1 and all four fans before sdram init
 *
 * Revision 1.15  2004/09/15 18:04:12  tsawyer
 * add multiple serial port support
 *
 * Revision 1.14  2004/09/03 15:27:51  tsawyer
 * All metrobox boards are at 66.66 sys clock
 *
 * Revision 1.13  2004/08/05 20:27:46  tsawyer
 * Remove system ace definitions, add net console support
 *
 * Revision 1.12  2004/07/29 20:00:13  tsawyer
 * Add i2c bus 1
 *
 * Revision 1.11  2004/07/21 13:44:18  tsawyer
 * SystemACE is out, CF direct to local bus is in
 *
 * Revision 1.10  2004/06/29 19:08:55  tsawyer
 * Add CONFIG_MISC_INIT_R
 *
 * Revision 1.9	 2004/06/28 21:30:53  tsawyer
 * Fix default BOOTARGS
 *
 * Revision 1.8	 2004/06/17 15:51:08  tsawyer
 * auto complete
 *
 * Revision 1.7	 2004/06/17 15:08:49  tsawyer
 * Add autocomplete
 *
 * Revision 1.6	 2004/06/15 12:33:57  tsawyer
 * debugging checkpoint
 *
 * Revision 1.5	 2004/06/12 19:48:28  tsawyer
 * Debugging checkpoint
 *
 * Revision 1.4	 2004/06/02 13:03:06  tsawyer
 * Fix eth addrs
 *
 * Revision 1.3	 2004/05/18 19:56:10  tsawyer
 * Change default bootcommand to pImage.metrobox
 *
 * Revision 1.2	 2004/05/18 14:13:44  tsawyer
 * Add bringup values for bootargs and bootcommand.
 * Remove definition of ipaddress and serverip addresses.
 *
 * Revision 1.1	 2004/04/16 15:08:54  tsawyer
 * Initial Revision
 *
 *
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_METROBOX		  1	     /* Board is Metrobox	*/
#define CONFIG_440GX		  1	     /* Specifc GX support	*/
#define CONFIG_440		  1	     /* ... PPC440 family	*/
#define CONFIG_4xx		  1	     /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFF80000

#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/

#define CONFIG_VERY_BIG_RAM 1
#define CONFIG_VERSION_VARIABLE

#define CONFIG_IDENT_STRING " Sandburst Metrobox"

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/

#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
#define CONFIG_SYS_FPGA_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM    1
#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE      0x2000	     /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#define CONFIG_BAUDRATE	      9600

#define CONFIG_SYS_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 * The DS1743 code assumes this condition (i.e. -- it assumes the base
 * address for the RTC registers is:
 *
 *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
 *
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_PPC4XX_CH1
#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
#undef	CONFIG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
#undef	CONFIG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/

#define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)

#define CONFIG_BOOTARGS	      "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
#define CONFIG_BOOTCOMMAND    "tftp 8000000 pImage.metrobox;bootm 8000000"
#define CONFIG_BOOTDELAY      5		    /* disable autoboot */

#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/

/*-----------------------------------------------------------------------
 * Networking
 *----------------------------------------------------------------------*/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII	      1		     /* MII PHY management	*/
#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_NETMASK	      255.255.0.0
#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_PING
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT


/* Include NetConsole support */
#define CONFIG_NETCONSOLE

/* Include auto complete with tabs */
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */

#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
#define CONFIG_SYS_PROMPT	      "MetroBox=> "  /* Monitor Command Prompt	*/

#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/


/*-----------------------------------------------------------------------
 * Console Buffer
 *----------------------------------------------------------------------*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
					     /* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/

/*-----------------------------------------------------------------------
 * Memory Test
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/

/*-----------------------------------------------------------------------
 * Compact Flash (in true IDE mode)
 *----------------------------------------------------------------------*/
#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/

#define CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */

#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
					    to get to the correct offset */
#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/

/*-----------------------------------------------------------------------
 * PCI
 *----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI			     /* include pci support	*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
#define CONFIG_KGDB_SER_INDEX 2		     /* kgdb serial port	*/
#endif

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */

#define CONFIG_SYS_HZ		      100	     /* decr freq: 1 ms ticks	*/


#endif	/* __CONFIG_H */
Commit	Line	Data
b79316f2 SR	1	/*
	2	* (C) Copyright 2004 Sandburst Corporation
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/************************************************************************
	24	* METROBOX.h - configuration Sandburst MetroBox
	25	***********************************************************************/
	26
	27	/*
	28	* $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
	29	*
	30	*
	31	* $Log: METROBOX.h,v $
	32	* Revision 1.21 2005/06/03 15:05:25 tsawyer
	33	* MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
	34	*
	35	* Revision 1.20 2005/04/11 20:51:11 tsawyer
	36	* fix ethernet
	37	*
	38	* Revision 1.19 2005/04/06 15:13:36 tsawyer
	39	* Update appropriate files to coincide with u-boot 1.1.3
	40	*
	41	* Revision 1.18 2005/03/10 14:16:02 tsawyer
	42	* add def'n for cis8201 short etch option.
	43	*
	44	* Revision 1.17 2005/03/09 19:49:51 tsawyer
	45	* Remove KGDB to allow use of 2nd serial port
	46	*
	47	* Revision 1.16 2004/12/02 19:00:23 tsawyer
	48	* Add misc_init_f to turn on i2c-1 and all four fans before sdram init
	49	*
	50	* Revision 1.15 2004/09/15 18:04:12 tsawyer
	51	* add multiple serial port support
	52	*
	53	* Revision 1.14 2004/09/03 15:27:51 tsawyer
	54	* All metrobox boards are at 66.66 sys clock
	55	*
	56	* Revision 1.13 2004/08/05 20:27:46 tsawyer
	57	* Remove system ace definitions, add net console support
	58	*
	59	* Revision 1.12 2004/07/29 20:00:13 tsawyer
	60	* Add i2c bus 1
	61	*
	62	* Revision 1.11 2004/07/21 13:44:18 tsawyer
	63	* SystemACE is out, CF direct to local bus is in
	64	*
65	* Revision 1.10 2004/06/29 19:08:55 tsawyer
66	* Add CONFIG_MISC_INIT_R
67	*
3d078ce6	68	* Revision 1.9 2004/06/28 21:30:53 tsawyer
b79316f2 SR	69	* Fix default BOOTARGS
b79316f2 SR	70	*
3d078ce6	71	* Revision 1.8 2004/06/17 15:51:08 tsawyer
b79316f2 SR	72	* auto complete
b79316f2 SR	73	*
3d078ce6	74	* Revision 1.7 2004/06/17 15:08:49 tsawyer
b79316f2 SR	75	* Add autocomplete
b79316f2 SR	76	*
3d078ce6	77	* Revision 1.6 2004/06/15 12:33:57 tsawyer
b79316f2 SR	78	* debugging checkpoint
b79316f2 SR	79	*
3d078ce6	80	* Revision 1.5 2004/06/12 19:48:28 tsawyer
b79316f2 SR	81	* Debugging checkpoint
b79316f2 SR	82	*
3d078ce6	83	* Revision 1.4 2004/06/02 13:03:06 tsawyer
b79316f2 SR	84	* Fix eth addrs
b79316f2 SR	85	*
3d078ce6	86	* Revision 1.3 2004/05/18 19:56:10 tsawyer
b79316f2 SR	87	* Change default bootcommand to pImage.metrobox
b79316f2 SR	88	*
3d078ce6	89	* Revision 1.2 2004/05/18 14:13:44 tsawyer
b79316f2 SR	90	* Add bringup values for bootargs and bootcommand.
	91	* Remove definition of ipaddress and serverip addresses.
	92	*
3d078ce6	93	* Revision 1.1 2004/04/16 15:08:54 tsawyer
b79316f2 SR	94	* Initial Revision
	95	*
	96	*
	97	*/
	98
	99	#ifndef __CONFIG_H
	100	#define __CONFIG_H
	101
	102	/*-----------------------------------------------------------------------
	103	* High Level Configuration Options
	104	----------------------------------------------------------------------/
3d078ce6 WD	105	#define CONFIG_METROBOX 1 /* Board is Metrobox */
3d078ce6 WD	106	#define CONFIG_440GX 1 /* Specifc GX support */
efa35cf1	107	#define CONFIG_440 1 /* ... PPC440 family */
3d078ce6	108	#define CONFIG_4xx 1 /* ... PPC4xx family */
b79316f2	109	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
3d078ce6 WD	110	#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
3d078ce6 WD	111	#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
2ae18241 WD	112
	113	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
	114
6d0f6bcf	115	#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
3d078ce6	116	#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
b79316f2 SR	117
	118	#define CONFIG_VERY_BIG_RAM 1
	119	#define CONFIG_VERSION_VARIABLE
	120
	121	#define CONFIG_IDENT_STRING " Sandburst Metrobox"
	122
	123	/*-----------------------------------------------------------------------
	124	* Base addresses -- Note these are effective addresses where the
	125	* actual resources get mapped (not physical addresses)
	126	----------------------------------------------------------------------/
6d0f6bcf JCPV	127	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	128	#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
	129	#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
	130	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
6d0f6bcf JCPV	131	#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
	132	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
	133
	134	#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
	135	#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
	136	#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
	137	#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
b79316f2 SR	138
	139	/*-----------------------------------------------------------------------
	140	* Initial RAM & stack pointer (placed in internal SRAM)
	141	----------------------------------------------------------------------/
6d0f6bcf JCPV	142	#define CONFIG_SYS_TEMP_STACK_OCM 1
	143	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	144	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
553f0982	145	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
b79316f2	146
25ddd1fb	147	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096	148	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
b79316f2	149
6d0f6bcf JCPV	150	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
6d0f6bcf JCPV	151	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
b79316f2 SR	152
	153	/*-----------------------------------------------------------------------
	154	* Serial Port
	155	----------------------------------------------------------------------/
550650dd SR	156	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	157	#define CONFIG_SYS_NS16550
	158	#define CONFIG_SYS_NS16550_SERIAL
	159	#define CONFIG_SYS_NS16550_REG_SIZE 1
	160	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
b79316f2 SR	161	#define CONFIG_BAUDRATE 9600
b79316f2 SR	162
6d0f6bcf	163	#define CONFIG_SYS_BAUDRATE_TABLE \
b79316f2 SR	164	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	165
	166	/*-----------------------------------------------------------------------
	167	* NVRAM/RTC
	168	*
	169	* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
	170	* The DS1743 code assumes this condition (i.e. -- it assumes the base
	171	* address for the RTC registers is:
	172	*
6d0f6bcf	173	* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
b79316f2 SR	174	*
b79316f2 SR	175	----------------------------------------------------------------------/
6d0f6bcf	176	#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
3d078ce6	177	#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
b79316f2 SR	178
	179	/*-----------------------------------------------------------------------
	180	* FLASH related
	181	----------------------------------------------------------------------/
6d0f6bcf JCPV	182	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
6d0f6bcf JCPV	183	#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
b79316f2	184
6d0f6bcf JCPV	185	#undef CONFIG_SYS_FLASH_CHECKSUM
	186	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
	187	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
b79316f2 SR	188
	189	/*-----------------------------------------------------------------------
	190	* DDR SDRAM
	191	----------------------------------------------------------------------/
3d078ce6 WD	192	#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
3d078ce6 WD	193	#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
b79316f2 SR	194
	195	/*-----------------------------------------------------------------------
	196	* I2C
	197	----------------------------------------------------------------------/
880540de DE	198	#define CONFIG_SYS_I2C
	199	#define CONFIG_SYS_I2C_PPC4XX
	200	#define CONFIG_SYS_I2C_PPC4XX_CH0
	201	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	202	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
	203	#define CONFIG_SYS_I2C_PPC4XX_CH1
	204	#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
	205	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
	206	#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
b79316f2 SR	207
	208	/*-----------------------------------------------------------------------
	209	* Environment
	210	----------------------------------------------------------------------/
9314cee6	211	#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
5a1aceb0	212	#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
bb1f8b4f	213	#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
3d078ce6	214	#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
b79316f2	215
0e8d1586	216	#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
6d0f6bcf	217	#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
b79316f2 SR	218
	219	#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
	220	#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000"
3d078ce6	221	#define CONFIG_BOOTDELAY 5 /* disable autoboot */
b79316f2	222
3d078ce6	223	#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
6d0f6bcf	224	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
b79316f2 SR	225
	226	/*-----------------------------------------------------------------------
	227	* Networking
	228	----------------------------------------------------------------------/
96e21f86	229	#define CONFIG_PPC4xx_EMAC
3d078ce6	230	#define CONFIG_MII 1 /* MII PHY management */
3d078ce6 WD	231	#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
	232	#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
	233	#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
	234	#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
b79316f2 SR	235	#define CONFIG_HAS_ETH0
	236	#define CONFIG_HAS_ETH1
	237	#define CONFIG_HAS_ETH2
	238	#define CONFIG_HAS_ETH3
d6c61aab	239	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
3d078ce6 WD	240	#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
	241	#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
	242	#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
b79316f2	243	#define CONFIG_PHY_RESET_DELAY 1000
3d078ce6 WD	244	#define CONFIG_NETMASK 255.255.0.0
	245	#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
	246	#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
6d0f6bcf	247	#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
b79316f2 SR	248
b79316f2 SR	249
659e2f67 JL	250	/*
	251	* BOOTP options
	252	*/
	253	#define CONFIG_BOOTP_BOOTFILESIZE
	254	#define CONFIG_BOOTP_BOOTPATH
	255	#define CONFIG_BOOTP_GATEWAY
	256	#define CONFIG_BOOTP_HOSTNAME
	257
	258
8353e139 JL	259	/*
	260	* Command line configuration.
	261	*/
	262	#include <config_cmd_default.h>
	263
	264	#define CONFIG_CMD_PCI
	265	#define CONFIG_CMD_IRQ
	266	#define CONFIG_CMD_I2C
	267	#define CONFIG_CMD_DHCP
	268	#define CONFIG_CMD_DATE
	269	#define CONFIG_CMD_BEDBUG
	270	#define CONFIG_CMD_PING
	271	#define CONFIG_CMD_DIAG
	272	#define CONFIG_CMD_MII
	273	#define CONFIG_CMD_NET
	274	#define CONFIG_CMD_ELF
	275	#define CONFIG_CMD_IDE
	276	#define CONFIG_CMD_FAT
b79316f2 SR	277
	278
	279	/* Include NetConsole support */
	280	#define CONFIG_NETCONSOLE
	281
	282	/* Include auto complete with tabs */
	283	#define CONFIG_AUTO_COMPLETE 1
8078f1a5	284	#define CONFIG_AUTO_COMPLETE 1
6d0f6bcf	285	#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
b79316f2	286
6d0f6bcf JCPV	287	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	288	#define CONFIG_SYS_PROMPT "MetroBox=> " /* Monitor Command Prompt */
b79316f2	289
6d0f6bcf	290	#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
b79316f2 SR	291
	292
	293	/*-----------------------------------------------------------------------
	294	* Console Buffer
	295	----------------------------------------------------------------------/
8353e139	296	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	297	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
b79316f2	298	#else
6d0f6bcf	299	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b79316f2	300	#endif
6d0f6bcf	301	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
3d078ce6	302	/* Print Buffer Size */
6d0f6bcf JCPV	303	#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
6d0f6bcf JCPV	304	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
b79316f2 SR	305
	306	/*-----------------------------------------------------------------------
	307	* Memory Test
	308	----------------------------------------------------------------------/
6d0f6bcf JCPV	309	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	310	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
b79316f2 SR	311
	312	/*-----------------------------------------------------------------------
	313	* Compact Flash (in true IDE mode)
	314	----------------------------------------------------------------------/
	315	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	316	#undef CONFIG_IDE_LED /* no led for ide supported */
	317
3d078ce6	318	#define CONFIG_IDE_RESET /* reset for ide supported */
6d0f6bcf JCPV	319	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
6d0f6bcf JCPV	320	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS1) / max. 1 drives per IDE bus */
b79316f2	321
6d0f6bcf JCPV	322	#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
	323	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	324	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	325	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
	326	#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
b79316f2	327
6d0f6bcf	328	#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
3d078ce6 WD	329	to get to the correct offset */
3d078ce6 WD	330	#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
b79316f2 SR	331
	332	/*-----------------------------------------------------------------------
	333	* PCI
	334	----------------------------------------------------------------------/
	335	/* General PCI */
3d078ce6	336	#define CONFIG_PCI /* include pci support */
842033e6	337	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
3d078ce6 WD	338	#define CONFIG_PCI_PNP /* do pci plug-and-play */
3d078ce6 WD	339	#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
6d0f6bcf	340	#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
b79316f2 SR	341
b79316f2 SR	342	/* Board-specific PCI */
6d0f6bcf	343	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
b79316f2	344
6d0f6bcf JCPV	345	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
6d0f6bcf JCPV	346	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
b79316f2 SR	347
	348	/*
	349	* For booting Linux, the board info and command line data
	350	* have to be in the first 8 MB of memory, since this is
	351	* the maximum mapped by the Linux kernel during initialization.
	352	*/
6d0f6bcf	353	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
b79316f2	354
8353e139	355	#if defined(CONFIG_CMD_KGDB)
3d078ce6 WD	356	#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
3d078ce6 WD	357	#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
b79316f2 SR	358	#endif
	359
	360	/*-----------------------------------------------------------------------
	361	* Miscellaneous configurable options
	362	----------------------------------------------------------------------/
3d078ce6	363	#undef CONFIG_WATCHDOG /* watchdog disabled */
6d0f6bcf JCPV	364	#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
6d0f6bcf JCPV	365	#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
b79316f2	366
6d0f6bcf	367	#define CONFIG_SYS_HZ 100 /* decr freq: 1 ms ticks */
b79316f2 SR	368
	369
	370	#endif /* __CONFIG_H */