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Commit | Line | Data |
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7d393aed WD |
1 | /* |
2 | * (C) Copyright 2001, 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
7d393aed WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /*********************************************************** | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | ***********************************************************/ | |
19 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
20 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
21 | #define CONFIG_MIP405 1 /* ...on a MIP405 board */ | |
2ae18241 WD |
22 | |
23 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 | |
24 | ||
f3e0de60 WD |
25 | /*********************************************************** |
26 | * Note that it may also be a MIP405T board which is a subset of the | |
27 | * MIP405 | |
28 | ***********************************************************/ | |
29 | /*********************************************************** | |
30 | * WARNING: | |
31 | * CONFIG_BOOT_PCI is only used for first boot-up and should | |
32 | * NOT be enabled for production bootloader | |
33 | ***********************************************************/ | |
8bde7f77 | 34 | /*#define CONFIG_BOOT_PCI 1*/ |
7d393aed WD |
35 | /*********************************************************** |
36 | * Clock | |
37 | ***********************************************************/ | |
38 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ | |
39 | ||
7d393aed | 40 | |
659e2f67 JL |
41 | /* |
42 | * BOOTP options | |
43 | */ | |
44 | #define CONFIG_BOOTP_BOOTFILESIZE | |
45 | #define CONFIG_BOOTP_BOOTPATH | |
46 | #define CONFIG_BOOTP_GATEWAY | |
47 | #define CONFIG_BOOTP_HOSTNAME | |
48 | ||
49 | ||
8353e139 JL |
50 | /* |
51 | * Command line configuration. | |
52 | */ | |
53 | #include <config_cmd_default.h> | |
54 | ||
55 | #define CONFIG_CMD_CACHE | |
56 | #define CONFIG_CMD_DATE | |
57 | #define CONFIG_CMD_DHCP | |
58 | #define CONFIG_CMD_EEPROM | |
59 | #define CONFIG_CMD_ELF | |
60 | #define CONFIG_CMD_FAT | |
61 | #define CONFIG_CMD_I2C | |
62 | #define CONFIG_CMD_IDE | |
63 | #define CONFIG_CMD_IRQ | |
64 | #define CONFIG_CMD_JFFS2 | |
65 | #define CONFIG_CMD_MII | |
66 | #define CONFIG_CMD_PCI | |
67 | #define CONFIG_CMD_PING | |
68 | #define CONFIG_CMD_REGINFO | |
69 | #define CONFIG_CMD_SAVES | |
70 | #define CONFIG_CMD_BSP | |
f3e0de60 | 71 | |
8353e139 JL |
72 | #if !defined(CONFIG_MIP405T) |
73 | #define CONFIG_CMD_USB | |
f3e0de60 WD |
74 | #endif |
75 | ||
7d393aed | 76 | |
6d0f6bcf | 77 | #define CONFIG_SYS_HUSH_PARSER |
7d393aed WD |
78 | /************************************************************** |
79 | * I2C Stuff: | |
80 | * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address | |
81 | * 0x53. | |
82 | * The Atmel EEPROM uses 16Bit addressing. | |
83 | ***************************************************************/ | |
84 | ||
85 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
d0b0dcaa | 86 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
87 | #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ |
88 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
7d393aed | 89 | |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ |
91 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
7d393aed | 92 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
93 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
94 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ | |
7d393aed WD |
95 | /* 64 byte page write mode using*/ |
96 | /* last 6 bits of the address */ | |
6d0f6bcf | 97 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
7d393aed WD |
98 | |
99 | ||
bb1f8b4f | 100 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
101 | #define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ |
102 | #define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ | |
7d393aed WD |
103 | |
104 | /*************************************************************** | |
105 | * Definitions for Serial Presence Detect EEPROM address | |
106 | * (to get SDRAM settings) | |
107 | ***************************************************************/ | |
f3e0de60 | 108 | /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 |
53677ef1 | 109 | #define SDRAM_EEPROM_READ_ADDRESS 0xA1 |
f3e0de60 | 110 | */ |
7d393aed WD |
111 | /************************************************************** |
112 | * Environment definitions | |
113 | **************************************************************/ | |
114 | #define CONFIG_BAUDRATE 9600 /* STD Baudrate */ | |
115 | #define CONFIG_BOOTDELAY 5 | |
116 | /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ | |
2afbe4ed | 117 | /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ |
53677ef1 | 118 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ |
7d393aed | 119 | |
3e38691e | 120 | #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ |
7d393aed WD |
121 | #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ |
122 | ||
123 | #define CONFIG_IPADDR 10.0.0.100 | |
124 | #define CONFIG_SERVERIP 10.0.0.1 | |
125 | #define CONFIG_PREBOOT | |
126 | /*************************************************************** | |
127 | * defines if the console is stored in the environment | |
128 | ***************************************************************/ | |
6d0f6bcf | 129 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ |
7d393aed WD |
130 | /*************************************************************** |
131 | * defines if an overwrite_console function exists | |
132 | *************************************************************/ | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
134 | #define CONFIG_SYS_CONSOLE_INFO_QUIET | |
7d393aed WD |
135 | /*************************************************************** |
136 | * defines if the overwrite_console should be stored in the | |
137 | * environment | |
138 | **************************************************************/ | |
6d0f6bcf | 139 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
7d393aed WD |
140 | |
141 | /************************************************************** | |
142 | * loads config | |
143 | *************************************************************/ | |
144 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 145 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
7d393aed WD |
146 | |
147 | #define CONFIG_MISC_INIT_R | |
148 | /*********************************************************** | |
149 | * Miscellaneous configurable options | |
150 | **********************************************************/ | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
152 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
8353e139 | 153 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 154 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
7d393aed | 155 | #else |
6d0f6bcf | 156 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
7d393aed | 157 | #endif |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
159 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
160 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
7d393aed | 161 | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
163 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ | |
7d393aed | 164 | |
550650dd SR |
165 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
166 | #define CONFIG_SYS_NS16550 | |
167 | #define CONFIG_SYS_NS16550_SERIAL | |
168 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
169 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
170 | ||
6d0f6bcf JCPV |
171 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
172 | #define CONFIG_SYS_BASE_BAUD 916667 | |
7d393aed WD |
173 | |
174 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 175 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
7d393aed WD |
176 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
177 | 57600, 115200, 230400, 460800, 921600 } | |
178 | ||
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
180 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
7d393aed | 181 | |
6d0f6bcf | 182 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
7d393aed WD |
183 | |
184 | /*----------------------------------------------------------------------- | |
185 | * PCI stuff | |
186 | *----------------------------------------------------------------------- | |
187 | */ | |
188 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
189 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
190 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
191 | ||
192 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 193 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
7d393aed WD |
194 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ |
195 | #define CONFIG_PCI_PNP /* pci plug-and-play */ | |
196 | /* resource configuration */ | |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
198 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ | |
199 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
200 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
201 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
202 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
203 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
204 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
7d393aed WD |
205 | |
206 | /*----------------------------------------------------------------------- | |
207 | * Start addresses for the final memory configuration | |
208 | * (Set up by the startup code) | |
6d0f6bcf | 209 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
7d393aed | 210 | */ |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
212 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 | |
213 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
214 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
215 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ | |
7d393aed WD |
216 | |
217 | /* | |
218 | * For booting Linux, the board info and command line data | |
219 | * have to be in the first 8 MB of memory, since this is | |
220 | * the maximum mapped by the Linux kernel during initialization. | |
221 | */ | |
6d0f6bcf | 222 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
7d393aed WD |
223 | /*----------------------------------------------------------------------- |
224 | * FLASH organization | |
225 | */ | |
39441b35 DM |
226 | #define CONFIG_SYS_UPDATE_FLASH_SIZE |
227 | #define CONFIG_SYS_FLASH_PROTECTION | |
228 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
7d393aed | 229 | |
39441b35 DM |
230 | #define CONFIG_SYS_FLASH_CFI |
231 | #define CONFIG_FLASH_CFI_DRIVER | |
232 | ||
233 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
234 | ||
235 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
236 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
7d393aed | 237 | |
700a0c64 WD |
238 | /* |
239 | * JFFS2 partitions | |
240 | * | |
241 | */ | |
242 | /* No command line, one static partition, whole device */ | |
68d7d651 | 243 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
244 | #define CONFIG_JFFS2_DEV "nor0" |
245 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
246 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
247 | ||
248 | /* mtdparts command line support */ | |
249 | /* Note: fake mtd_id used, no linux mtd map file */ | |
250 | /* | |
68d7d651 | 251 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
252 | #define MTDIDS_DEFAULT "nor0=mip405-0" |
253 | #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" | |
254 | */ | |
7d393aed | 255 | |
63e73c9a WD |
256 | /*----------------------------------------------------------------------- |
257 | * Logbuffer Configuration | |
258 | */ | |
53677ef1 | 259 | #undef CONFIG_LOGBUFFER /* supported but not enabled */ |
63e73c9a WD |
260 | /*----------------------------------------------------------------------- |
261 | * Bootcountlimit Configuration | |
262 | */ | |
263 | #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */ | |
264 | ||
265 | /*----------------------------------------------------------------------- | |
266 | * POST Configuration | |
267 | */ | |
268 | #if 0 /* enable this if POST is desired (is supported but not enabled) */ | |
6d0f6bcf JCPV |
269 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
270 | CONFIG_SYS_POST_CPU | \ | |
271 | CONFIG_SYS_POST_RTC | \ | |
272 | CONFIG_SYS_POST_I2C) | |
63e73c9a WD |
273 | |
274 | #endif | |
7d393aed WD |
275 | /* |
276 | * Init Memory Controller: | |
277 | */ | |
7205e407 WD |
278 | #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ |
279 | #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ | |
280 | /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ | |
281 | #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ | |
7d393aed | 282 | |
c837dcb1 | 283 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
39441b35 | 284 | #define CONFIG_BOARD_EARLY_INIT_R |
7d393aed WD |
285 | |
286 | /* Peripheral Bus Mapping */ | |
287 | #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ | |
288 | #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/ | |
289 | #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ | |
290 | ||
291 | #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 | |
53677ef1 | 292 | #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 |
7d393aed WD |
293 | |
294 | ||
7d393aed WD |
295 | /*----------------------------------------------------------------------- |
296 | * Definitions for initial stack pointer and data area (in On Chip SRAM) | |
297 | */ | |
6d0f6bcf JCPV |
298 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
299 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 | |
300 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
301 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ | |
553f0982 | 302 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ |
25ddd1fb | 303 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
63e73c9a | 304 | /* reserve some memory for POST and BOOT limit info */ |
6d0f6bcf | 305 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) |
63e73c9a | 306 | |
63e73c9a | 307 | #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ |
6d0f6bcf | 308 | #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12) |
63e73c9a | 309 | #endif |
7d393aed | 310 | |
7d393aed WD |
311 | /*********************************************************************** |
312 | * External peripheral base address | |
313 | ***********************************************************************/ | |
6d0f6bcf | 314 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 |
7d393aed WD |
315 | |
316 | /*********************************************************************** | |
317 | * Last Stage Init | |
318 | ***********************************************************************/ | |
319 | #define CONFIG_LAST_STAGE_INIT | |
320 | /************************************************************ | |
321 | * Ethernet Stuff | |
322 | ***********************************************************/ | |
96e21f86 | 323 | #define CONFIG_PPC4xx_EMAC |
7d393aed WD |
324 | #define CONFIG_MII 1 /* MII PHY management */ |
325 | #define CONFIG_PHY_ADDR 1 /* PHY address */ | |
63e73c9a WD |
326 | #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ |
327 | #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ | |
7d393aed WD |
328 | /************************************************************ |
329 | * RTC | |
330 | ***********************************************************/ | |
331 | #define CONFIG_RTC_MC146818 | |
332 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
333 | ||
334 | /************************************************************ | |
335 | * IDE/ATA stuff | |
336 | ************************************************************/ | |
f3e0de60 | 337 | #if defined(CONFIG_MIP405T) |
6d0f6bcf | 338 | #define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ |
f3e0de60 | 339 | #else |
6d0f6bcf | 340 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
f3e0de60 WD |
341 | #endif |
342 | ||
6d0f6bcf | 343 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ |
7d393aed | 344 | |
6d0f6bcf JCPV |
345 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */ |
346 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ | |
347 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ | |
348 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ | |
349 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ | |
350 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ | |
7d393aed WD |
351 | |
352 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
353 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
354 | #define CONFIG_IDE_RESET /* reset for ide supported... */ | |
355 | #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ | |
7205e407 | 356 | #define CONFIG_SUPPORT_VFAT |
7d393aed WD |
357 | /************************************************************ |
358 | * ATAPI support (experimental) | |
359 | ************************************************************/ | |
360 | #define CONFIG_ATAPI /* enable ATAPI Support */ | |
361 | ||
7d393aed WD |
362 | /************************************************************ |
363 | * DISK Partition support | |
364 | ************************************************************/ | |
365 | #define CONFIG_DOS_PARTITION | |
366 | #define CONFIG_MAC_PARTITION | |
367 | #define CONFIG_ISO_PARTITION /* Experimental */ | |
368 | ||
7d393aed WD |
369 | /************************************************************ |
370 | * Keyboard support | |
371 | ************************************************************/ | |
372 | #undef CONFIG_ISA_KEYBOARD | |
373 | ||
374 | /************************************************************ | |
375 | * Video support | |
376 | ************************************************************/ | |
377 | #define CONFIG_VIDEO /*To enable video controller support */ | |
378 | #define CONFIG_VIDEO_CT69000 | |
379 | #define CONFIG_CFB_CONSOLE | |
380 | #define CONFIG_VIDEO_LOGO | |
381 | #define CONFIG_CONSOLE_EXTRA_INFO | |
382 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
383 | #define CONFIG_VIDEO_SW_CURSOR | |
384 | #undef CONFIG_VIDEO_ONBOARD | |
385 | /************************************************************ | |
386 | * USB support EXPERIMENTAL | |
387 | ************************************************************/ | |
f3e0de60 | 388 | #if !defined(CONFIG_MIP405T) |
7d393aed WD |
389 | #define CONFIG_USB_UHCI |
390 | #define CONFIG_USB_KEYBOARD | |
391 | #define CONFIG_USB_STORAGE | |
392 | ||
393 | /* Enable needed helper functions */ | |
52cb4d4f | 394 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
f3e0de60 | 395 | #endif |
7d393aed WD |
396 | /************************************************************ |
397 | * Debug support | |
398 | ************************************************************/ | |
8353e139 | 399 | #if defined(CONFIG_CMD_KGDB) |
7d393aed WD |
400 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
401 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
402 | #endif | |
403 | ||
a2663ea4 WD |
404 | /************************************************************ |
405 | * support BZIP2 compression | |
406 | ************************************************************/ | |
407 | #define CONFIG_BZIP2 1 | |
408 | ||
7d393aed WD |
409 | /************************************************************ |
410 | * Ident | |
411 | ************************************************************/ | |
f3e0de60 | 412 | |
7d393aed | 413 | #define VERSION_TAG "released" |
f3e0de60 WD |
414 | #if !defined(CONFIG_MIP405T) |
415 | #define CONFIG_ISO_STRING "MEV-10072-001" | |
416 | #else | |
417 | #define CONFIG_ISO_STRING "MEV-10082-001" | |
418 | #endif | |
419 | ||
420 | #if !defined(CONFIG_BOOT_PCI) | |
421 | #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG | |
422 | #else | |
423 | #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version" | |
424 | #endif | |
7d393aed WD |
425 | |
426 | ||
427 | #endif /* __CONFIG_H */ |