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e2211743 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Stuart Hughes <stuarth@lineo.com> | |
4 | * This file is based on similar values for other boards found in other | |
5 | * U-Boot config files, and some that I found in the mpc8260ads manual. | |
6 | * | |
7 | * Note: my board is a PILOT rev. | |
8 | * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. | |
9 | * | |
04a85b3b | 10 | * (C) Copyright 2003-2004 Arabella Software Ltd. |
cceb871f | 11 | * Yuli Barcohen <yuli@arabellasw.com> |
2535d602 | 12 | * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2. |
ef5a9672 | 13 | * Ported to PQ2FADS-ZU and PQ2FADS-VR boards. |
04a85b3b | 14 | * Ported to MPC8272ADS board. |
cceb871f | 15 | * |
716c1dcb | 16 | * Copyright (c) 2005 MontaVista Software, Inc. |
1972dc0a WD |
17 | * Vitaly Bordug <vbordug@ru.mvista.com> |
18 | * Added support for PCI bridge on MPC8272ADS | |
19 | * | |
c73ed274 SW |
20 | * Copyright (C) Freescale Semiconductor, Inc. 2006-2009. |
21 | * | |
3765b3e7 | 22 | * SPDX-License-Identifier: GPL-2.0+ |
e2211743 WD |
23 | */ |
24 | ||
e2211743 WD |
25 | #ifndef __CONFIG_H |
26 | #define __CONFIG_H | |
27 | ||
28 | /* | |
29 | * High Level Configuration Options | |
30 | * (easy to change) | |
31 | */ | |
32 | ||
04a85b3b | 33 | #define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */ |
e2211743 | 34 | |
2ae18241 WD |
35 | #ifndef CONFIG_SYS_TEXT_BASE |
36 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ | |
37 | #endif | |
38 | ||
9c4c5ae3 JL |
39 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
40 | ||
901787d6 WD |
41 | /* |
42 | * Figure out if we are booting low via flash HRCW or high via the BCSR. | |
43 | */ | |
14d0a02a | 44 | #if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ |
6d0f6bcf | 45 | # define CONFIG_SYS_LOWBOOT 1 |
901787d6 WD |
46 | #endif |
47 | ||
2535d602 | 48 | /* ADS flavours */ |
6d0f6bcf JCPV |
49 | #define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */ |
50 | #define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */ | |
51 | #define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */ | |
52 | #define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */ | |
2535d602 WD |
53 | |
54 | #ifndef CONFIG_ADSTYPE | |
6d0f6bcf | 55 | #define CONFIG_ADSTYPE CONFIG_SYS_8260ADS |
2535d602 WD |
56 | #endif /* CONFIG_ADSTYPE */ |
57 | ||
6d0f6bcf | 58 | #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS |
04a85b3b | 59 | #define CONFIG_MPC8272 1 |
8701ecef SW |
60 | #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS |
61 | /* | |
62 | * Actually MPC8275, but the code is littered with ifdefs that | |
63 | * apply to both, or which use this ifdef to assume board-specific | |
64 | * details. :-( | |
65 | */ | |
66 | #define CONFIG_MPC8272 1 | |
04a85b3b WD |
67 | #else |
68 | #define CONFIG_MPC8260 1 | |
6d0f6bcf | 69 | #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ |
04a85b3b | 70 | |
c837dcb1 | 71 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
004eca0c | 72 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
e2211743 WD |
73 | |
74 | /* allow serial and ethaddr to be overwritten */ | |
75 | #define CONFIG_ENV_OVERWRITE | |
76 | ||
77 | /* | |
78 | * select serial console configuration | |
79 | * | |
80 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
81 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
82 | * for SCC). | |
83 | * | |
84 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
85 | * defined elsewhere (for example, on the cogent platform, there are serial | |
86 | * ports on the motherboard which are used for the serial console - see | |
87 | * cogent/cma101/serial.[ch]). | |
88 | */ | |
89 | #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
90 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
91 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
92 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
93 | ||
94 | /* | |
95 | * select ethernet configuration | |
96 | * | |
97 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
98 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
99 | * for FCC) | |
100 | * | |
101 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 102 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
e2211743 WD |
103 | */ |
104 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
105 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
106 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
e2211743 | 107 | |
48b42616 | 108 | #ifdef CONFIG_ETHER_ON_FCC |
e2211743 | 109 | |
48b42616 WD |
110 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ |
111 | ||
04a85b3b WD |
112 | #if CONFIG_ETHER_INDEX == 1 |
113 | ||
6d0f6bcf | 114 | # define CONFIG_SYS_PHY_ADDR 0 |
d4590da4 MF |
115 | # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) |
116 | # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) | |
04a85b3b WD |
117 | |
118 | #elif CONFIG_ETHER_INDEX == 2 | |
119 | ||
6d0f6bcf JCPV |
120 | #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */ |
121 | # define CONFIG_SYS_PHY_ADDR 3 | |
d4590da4 | 122 | # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16) |
04a85b3b | 123 | #else /* RxCLK is CLK13, TxCLK is CLK14 */ |
6d0f6bcf | 124 | # define CONFIG_SYS_PHY_ADDR 0 |
d4590da4 | 125 | # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
6d0f6bcf | 126 | #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ |
04a85b3b | 127 | |
d4590da4 | 128 | # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
e2211743 WD |
129 | |
130 | #endif /* CONFIG_ETHER_INDEX */ | |
131 | ||
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */ |
133 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */ | |
04a85b3b | 134 | |
48b42616 WD |
135 | #define CONFIG_MII /* MII PHY management */ |
136 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
137 | /* | |
138 | * GPIO pins used for bit-banged MII communications | |
139 | */ | |
140 | #define MDIO_PORT 2 /* Port C */ | |
be225442 LCM |
141 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
142 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
143 | #define MDC_DECLARE MDIO_DECLARE | |
48b42616 | 144 | |
6d0f6bcf JCPV |
145 | #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS |
146 | #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */ | |
147 | #define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */ | |
04a85b3b | 148 | #else |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */ |
150 | #define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */ | |
151 | #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ | |
04a85b3b | 152 | |
6d0f6bcf JCPV |
153 | #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) |
154 | #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) | |
155 | #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) | |
04a85b3b | 156 | |
6d0f6bcf JCPV |
157 | #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ |
158 | else iop->pdat &= ~CONFIG_SYS_MDIO_PIN | |
48b42616 | 159 | |
6d0f6bcf JCPV |
160 | #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ |
161 | else iop->pdat &= ~CONFIG_SYS_MDC_PIN | |
48b42616 WD |
162 | |
163 | #define MIIDELAY udelay(1) | |
164 | ||
165 | #endif /* CONFIG_ETHER_ON_FCC */ | |
166 | ||
6d0f6bcf | 167 | #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS |
04a85b3b | 168 | #undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */ |
2535d602 | 169 | #else |
e2211743 | 170 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
172 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
e2211743 | 173 | |
db2f721f | 174 | #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) |
2b792afc | 175 | #define CONFIG_SPD_ADDR 0x50 |
db2f721f | 176 | #endif |
6d0f6bcf | 177 | #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */ |
e2211743 | 178 | |
1972dc0a | 179 | /*PCI*/ |
8701ecef | 180 | #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS |
1972dc0a | 181 | #define CONFIG_PCI |
842033e6 | 182 | #define CONFIG_PCI_INDIRECT_BRIDGE |
1972dc0a WD |
183 | #define CONFIG_PCI_PNP |
184 | #define CONFIG_PCI_BOOTDELAY 0 | |
185 | #define CONFIG_PCI_SCAN_SHOW | |
186 | #endif | |
187 | ||
db2f721f | 188 | #ifndef CONFIG_SDRAM_PBI |
2b792afc | 189 | #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ |
db2f721f WD |
190 | #endif |
191 | ||
192 | #ifndef CONFIG_8260_CLKIN | |
6d0f6bcf | 193 | #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS |
2535d602 WD |
194 | #define CONFIG_8260_CLKIN 100000000 /* in Hz */ |
195 | #else | |
ef5a9672 | 196 | #define CONFIG_8260_CLKIN 66000000 /* in Hz */ |
db2f721f | 197 | #endif |
2535d602 WD |
198 | #endif |
199 | ||
e1599e83 | 200 | #define CONFIG_BAUDRATE 115200 |
e2211743 | 201 | |
0e6989b9 MI |
202 | #define CONFIG_OF_LIBFDT 1 |
203 | #define CONFIG_OF_BOARD_SETUP 1 | |
204 | #if defined(CONFIG_OF_LIBFDT) | |
0e6989b9 MI |
205 | #define OF_TBCLK (bd->bi_busfreq / 4) |
206 | #endif | |
207 | ||
659e2f67 JL |
208 | /* |
209 | * BOOTP options | |
210 | */ | |
211 | #define CONFIG_BOOTP_BOOTFILESIZE | |
212 | #define CONFIG_BOOTP_BOOTPATH | |
213 | #define CONFIG_BOOTP_GATEWAY | |
214 | #define CONFIG_BOOTP_HOSTNAME | |
215 | ||
216 | ||
1cc4c458 JL |
217 | /* |
218 | * Command line configuration. | |
219 | */ | |
4e620410 JCPV |
220 | #include <config_cmd_default.h> |
221 | ||
222 | #define CONFIG_CMD_ASKENV | |
223 | #define CONFIG_CMD_CACHE | |
224 | #define CONFIG_CMD_CDP | |
225 | #define CONFIG_CMD_DHCP | |
226 | #define CONFIG_CMD_DIAG | |
227 | #define CONFIG_CMD_I2C | |
228 | #define CONFIG_CMD_IMMAP | |
229 | #define CONFIG_CMD_IRQ | |
230 | #define CONFIG_CMD_JFFS2 | |
231 | #define CONFIG_CMD_MII | |
232 | #define CONFIG_CMD_PCI | |
233 | #define CONFIG_CMD_PING | |
234 | #define CONFIG_CMD_PORTIO | |
235 | #define CONFIG_CMD_REGINFO | |
236 | #define CONFIG_CMD_SAVES | |
237 | #define CONFIG_CMD_SDRAM | |
238 | ||
1cc4c458 | 239 | #undef CONFIG_CMD_XIMG |
2535d602 | 240 | |
6d0f6bcf | 241 | #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS |
1cc4c458 JL |
242 | #undef CONFIG_CMD_SDRAM |
243 | #undef CONFIG_CMD_I2C | |
244 | ||
6d0f6bcf | 245 | #elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS |
1cc4c458 JL |
246 | #undef CONFIG_CMD_SDRAM |
247 | #undef CONFIG_CMD_I2C | |
1cc4c458 | 248 | |
2535d602 | 249 | #else |
1cc4c458 JL |
250 | #undef CONFIG_CMD_PCI |
251 | ||
6d0f6bcf | 252 | #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */ |
e2211743 | 253 | |
1cc4c458 | 254 | |
04a85b3b WD |
255 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
256 | #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ | |
257 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2" | |
e2211743 | 258 | |
8353e139 | 259 | #if defined(CONFIG_CMD_KGDB) |
e2211743 WD |
260 | #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
261 | #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ | |
262 | #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ | |
263 | #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ | |
264 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ | |
265 | #endif | |
266 | ||
ef5a9672 | 267 | #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ |
2b792afc | 268 | #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ |
e2211743 WD |
269 | |
270 | /* | |
271 | * Miscellaneous configurable options | |
272 | */ | |
6d0f6bcf | 273 | #define CONFIG_SYS_HUSH_PARSER |
6d0f6bcf | 274 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
8353e139 | 275 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 276 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
e2211743 | 277 | #else |
6d0f6bcf | 278 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e2211743 | 279 | #endif |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
281 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
282 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
e2211743 | 283 | |
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
285 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
e2211743 | 286 | |
6d0f6bcf | 287 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
e2211743 | 288 | |
6d0f6bcf | 289 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
e2211743 | 290 | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_FLASH_BASE 0xff800000 |
292 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
293 | #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */ | |
294 | #define CONFIG_SYS_FLASH_SIZE 8 | |
295 | #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ | |
296 | #define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ | |
297 | #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ | |
298 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ | |
299 | #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
8564acf9 | 300 | |
700a0c64 WD |
301 | /* |
302 | * JFFS2 partitions | |
303 | * | |
304 | * Note: fake mtd_id used, no linux mtd map file | |
305 | */ | |
306 | #define MTDIDS_DEFAULT "nor0=mpc8260ads-0" | |
307 | #define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)" | |
6d0f6bcf | 308 | #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS |
e2211743 WD |
309 | |
310 | /* this is stuff came out of the Motorola docs */ | |
6d0f6bcf JCPV |
311 | #ifndef CONFIG_SYS_LOWBOOT |
312 | #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 | |
901787d6 | 313 | #endif |
e2211743 | 314 | |
6d0f6bcf JCPV |
315 | #define CONFIG_SYS_IMMR 0xF0000000 |
316 | #define CONFIG_SYS_BCSR 0xF4500000 | |
8701ecef | 317 | #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS |
6d0f6bcf | 318 | #define CONFIG_SYS_PCI_INT 0xF8200000 |
1972dc0a | 319 | #endif |
6d0f6bcf JCPV |
320 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
321 | #define CONFIG_SYS_LSDRAM_BASE 0xFD000000 | |
e2211743 WD |
322 | |
323 | #define RS232EN_1 0x02000002 | |
324 | #define RS232EN_2 0x01000001 | |
2535d602 WD |
325 | #define FETHIEN1 0x08000008 |
326 | #define FETH1_RST 0x04000004 | |
04a85b3b | 327 | #define FETHIEN2 0x10000000 |
2535d602 | 328 | #define FETH2_RST 0x08000000 |
326428cc | 329 | #define BCSR_PCI_MODE 0x01000000 |
e2211743 | 330 | |
6d0f6bcf | 331 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 332 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ |
25ddd1fb | 333 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 334 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e2211743 | 335 | |
6d0f6bcf | 336 | #ifdef CONFIG_SYS_LOWBOOT |
901787d6 | 337 | /* PQ2FADS flash HRCW = 0x0EB4B645 */ |
6d0f6bcf | 338 | #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ |
901787d6 WD |
339 | ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\ |
340 | ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ | |
341 | ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ | |
342 | ) | |
343 | #else | |
344 | /* PQ2FADS BCSR HRCW = 0x0CB23645 */ | |
6d0f6bcf | 345 | #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ |
e2211743 WD |
346 | ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\ |
347 | ( HRCW_BMS | HRCW_APPC10 ) |\ | |
348 | ( HRCW_MODCK_H0101 ) \ | |
349 | ) | |
901787d6 | 350 | #endif |
e2211743 | 351 | /* no slaves */ |
6d0f6bcf JCPV |
352 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
353 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
354 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
355 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
356 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
357 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
358 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
e2211743 | 359 | |
14d0a02a | 360 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
d98b0523 | 361 | |
6d0f6bcf JCPV |
362 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
363 | # define CONFIG_SYS_RAMBOOT | |
e2211743 WD |
364 | #endif |
365 | ||
6d0f6bcf JCPV |
366 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
367 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
e2211743 | 368 | |
ef5a9672 | 369 | #ifdef CONFIG_BZIP2 |
6d0f6bcf | 370 | #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ |
ef5a9672 | 371 | #else |
6d0f6bcf | 372 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ |
ef5a9672 WD |
373 | #endif /* CONFIG_BZIP2 */ |
374 | ||
6d0f6bcf | 375 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 376 | # define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 377 | # define CONFIG_ENV_SECT_SIZE 0x40000 |
6d0f6bcf | 378 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE) |
e2211743 | 379 | #else |
9314cee6 | 380 | # define CONFIG_ENV_IS_IN_NVRAM 1 |
6d0f6bcf | 381 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 382 | # define CONFIG_ENV_SIZE 0x200 |
6d0f6bcf | 383 | #endif /* CONFIG_SYS_RAMBOOT */ |
e2211743 | 384 | |
6d0f6bcf | 385 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
1cc4c458 | 386 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 387 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
e2211743 WD |
388 | #endif |
389 | ||
6d0f6bcf JCPV |
390 | #define CONFIG_SYS_HID0_INIT 0 |
391 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) | |
e2211743 | 392 | |
6d0f6bcf | 393 | #define CONFIG_SYS_HID2 0 |
e2211743 | 394 | |
6d0f6bcf JCPV |
395 | #define CONFIG_SYS_SYPCR 0xFFFFFFC3 |
396 | #define CONFIG_SYS_BCR 0x100C0000 | |
397 | #define CONFIG_SYS_SIUMCR 0x0A200000 | |
398 | #define CONFIG_SYS_SCCR SCCR_DFBRG01 | |
399 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801) | |
400 | #define CONFIG_SYS_OR0_PRELIM 0xFF800876 | |
401 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801) | |
402 | #define CONFIG_SYS_OR1_PRELIM 0xFFFF8010 | |
e2211743 | 403 | |
1972dc0a WD |
404 | /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ |
405 | ||
6d0f6bcf JCPV |
406 | #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS |
407 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */ | |
408 | #define CONFIG_SYS_OR3_PRELIM 0xFFFF8010 | |
8701ecef SW |
409 | #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS |
410 | #define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */ | |
411 | #define CONFIG_SYS_OR8_PRELIM 0xFFFF8010 | |
1972dc0a WD |
412 | #endif |
413 | ||
6d0f6bcf JCPV |
414 | #define CONFIG_SYS_RMR RMR_CSRE |
415 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
416 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
417 | #define CONFIG_SYS_RCCR 0 | |
418 | ||
419 | #if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS) | |
420 | #undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */ | |
421 | #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */ | |
422 | ||
423 | #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS | |
424 | #define CONFIG_SYS_OR2 0xFE002EC0 | |
425 | #define CONFIG_SYS_PSDMR 0x824B36A3 | |
426 | #define CONFIG_SYS_PSRT 0x13 | |
427 | #define CONFIG_SYS_LSDMR 0x828737A3 | |
428 | #define CONFIG_SYS_LSRT 0x13 | |
429 | #define CONFIG_SYS_MPTPR 0x2800 | |
430 | #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS | |
431 | #define CONFIG_SYS_OR2 0xFC002CC0 | |
432 | #define CONFIG_SYS_PSDMR 0x834E24A3 | |
433 | #define CONFIG_SYS_PSRT 0x13 | |
434 | #define CONFIG_SYS_MPTPR 0x2800 | |
2535d602 | 435 | #else |
6d0f6bcf JCPV |
436 | #define CONFIG_SYS_OR2 0xFF000CA0 |
437 | #define CONFIG_SYS_PSDMR 0x016EB452 | |
438 | #define CONFIG_SYS_PSRT 0x21 | |
439 | #define CONFIG_SYS_LSDMR 0x0086A522 | |
440 | #define CONFIG_SYS_LSRT 0x21 | |
441 | #define CONFIG_SYS_MPTPR 0x1900 | |
442 | #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ | |
e2211743 | 443 | |
6d0f6bcf | 444 | #define CONFIG_SYS_RESET_ADDRESS 0x04400000 |
e2211743 | 445 | |
8701ecef | 446 | #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS |
1972dc0a WD |
447 | |
448 | /* PCI Memory map (if different from default map */ | |
6d0f6bcf JCPV |
449 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ |
450 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ | |
451 | #define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ | |
1972dc0a WD |
452 | PICMR_PREFETCH_EN) |
453 | ||
454 | /* | |
455 | * These are the windows that allow the CPU to access PCI address space. | |
456 | * All three PCI master windows, which allow the CPU to access PCI | |
457 | * prefetch, non prefetch, and IO space (see below), must all fit within | |
458 | * these windows. | |
459 | */ | |
460 | ||
1972dc0a WD |
461 | /* |
462 | * Master window that allows the CPU to access PCI Memory (prefetch). | |
463 | * This window will be setup with the second set of Outbound ATU registers | |
464 | * in the bridge. | |
465 | */ | |
466 | ||
6d0f6bcf JCPV |
467 | #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ |
468 | #define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ | |
469 | #define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL | |
470 | #define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ | |
471 | #define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) | |
1972dc0a WD |
472 | |
473 | /* | |
474 | * Master window that allows the CPU to access PCI Memory (non-prefetch). | |
475 | * This window will be setup with the second set of Outbound ATU registers | |
476 | * in the bridge. | |
477 | */ | |
478 | ||
6d0f6bcf JCPV |
479 | #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ |
480 | #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ | |
481 | #define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL | |
482 | #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ | |
483 | #define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) | |
1972dc0a WD |
484 | |
485 | /* | |
486 | * Master window that allows the CPU to access PCI IO space. | |
487 | * This window will be setup with the first set of Outbound ATU registers | |
488 | * in the bridge. | |
489 | */ | |
490 | ||
6d0f6bcf JCPV |
491 | #define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ |
492 | #define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ | |
493 | #define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL | |
494 | #define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ | |
495 | #define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) | |
1972dc0a WD |
496 | |
497 | ||
498 | /* PCIBR0 - for PCI IO*/ | |
6d0f6bcf JCPV |
499 | #define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */ |
500 | #define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ | |
1972dc0a | 501 | /* PCIBR1 - prefetch and non-prefetch regions joined together */ |
6d0f6bcf JCPV |
502 | #define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL |
503 | #define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U) | |
1972dc0a WD |
504 | |
505 | #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/ | |
506 | ||
42f9ebff SW |
507 | #define CONFIG_HAS_ETH0 |
508 | ||
6d0f6bcf | 509 | #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS |
c570b2fd | 510 | #define CONFIG_HAS_ETH1 |
c2d0ab4d WD |
511 | #endif |
512 | ||
c73ed274 SW |
513 | #define CONFIG_NETDEV eth0 |
514 | #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ | |
515 | ||
c73ed274 | 516 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d | 517 | "netdev=" __stringify(CONFIG_NETDEV) "\0" \ |
c73ed274 | 518 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
519 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
520 | " +$filesize; " \ | |
521 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
522 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
523 | " $filesize; " \ | |
524 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
525 | " +$filesize; " \ | |
526 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
527 | " $filesize\0" \ | |
c73ed274 SW |
528 | "fdtaddr=400000\0" \ |
529 | "console=ttyCPM0\0" \ | |
530 | "setbootargs=setenv bootargs " \ | |
531 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
532 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
533 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
534 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" | |
535 | ||
536 | #define CONFIG_NFSBOOTCOMMAND \ | |
537 | "setenv rootdev /dev/nfs;" \ | |
538 | "run setipargs;" \ | |
539 | "tftp $loadaddr $bootfile;" \ | |
540 | "tftp $fdtaddr $fdtfile;" \ | |
541 | "bootm $loadaddr - $fdtaddr" | |
542 | ||
543 | #define CONFIG_RAMBOOTCOMMAND \ | |
544 | "setenv rootdev /dev/ram;" \ | |
545 | "run setbootargs;" \ | |
546 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
547 | "tftp $loadaddr $bootfile;" \ | |
548 | "tftp $fdtaddr $fdtfile;" \ | |
549 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
550 | ||
e2211743 | 551 | #endif /* __CONFIG_H */ |